Search

Kenneth S. Kim

Examiner (ID: 328)

Most Active Art Unit
2111
Art Unit(s)
2783, 2315, 2181, 2183, 2784, 2111, 1107, 2302, 2185
Total Applications
1565
Issued Applications
1268
Pending Applications
37
Abandoned Applications
262

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3768634 [patent_doc_number] => 05721959 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-24 [patent_title] => 'Information processing apparatus for pattern editing using logic relationship representative patterns' [patent_app_type] => 1 [patent_app_number] => 8/347173 [patent_app_country] => US [patent_app_date] => 1994-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 49 [patent_no_of_words] => 12622 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/721/05721959.pdf [firstpage_image] =>[orig_patent_app_number] => 347173 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/347173
Information processing apparatus for pattern editing using logic relationship representative patterns Nov 21, 1994 Issued
Array ( [id] => 3600065 [patent_doc_number] => 05497471 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-05 [patent_title] => 'High performance computer system which minimizes latency between many high performance processors and a large amount of shared memory' [patent_app_type] => 1 [patent_app_number] => 8/339512 [patent_app_country] => US [patent_app_date] => 1994-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 21 [patent_no_of_words] => 5315 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 366 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/497/05497471.pdf [firstpage_image] =>[orig_patent_app_number] => 339512 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/339512
High performance computer system which minimizes latency between many high performance processors and a large amount of shared memory Nov 13, 1994 Issued
08/340791 INFORMATION EXCHANGE METHOD AND APPARATUS INCLUDING A DIALOGUE SYSTEM FOR FORMULATING SENTENCES FOR SUBMISSION TO AN ALTERNATE SYSTEM Nov 10, 1994 Abandoned
08/335263 DESYNCHRONISING INFORMATION AT THE EXIT OF A SYNCHRONOUS TRANSPORT NETWORK Nov 6, 1994 Abandoned
Array ( [id] => 3612202 [patent_doc_number] => 05559977 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-24 [patent_title] => 'Method and apparatus for executing floating point (FP) instruction pairs in a pipelined processor by stalling the following FP instructions in an execution stage' [patent_app_type] => 1 [patent_app_number] => 8/328395 [patent_app_country] => US [patent_app_date] => 1994-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 6202 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 294 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/559/05559977.pdf [firstpage_image] =>[orig_patent_app_number] => 328395 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/328395
Method and apparatus for executing floating point (FP) instruction pairs in a pipelined processor by stalling the following FP instructions in an execution stage Oct 23, 1994 Issued
Array ( [id] => 3676601 [patent_doc_number] => 05598541 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-28 [patent_title] => 'Node loop port communication interface super core for fibre channel' [patent_app_type] => 1 [patent_app_number] => 8/329032 [patent_app_country] => US [patent_app_date] => 1994-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 10411 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 346 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/598/05598541.pdf [firstpage_image] =>[orig_patent_app_number] => 329032 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/329032
Node loop port communication interface super core for fibre channel Oct 23, 1994 Issued
Array ( [id] => 3621420 [patent_doc_number] => 05590314 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-31 [patent_title] => 'Apparatus for sending message via cable between programs and performing automatic operation in response to sent message' [patent_app_type] => 1 [patent_app_number] => 8/320676 [patent_app_country] => US [patent_app_date] => 1994-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 4733 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/590/05590314.pdf [firstpage_image] =>[orig_patent_app_number] => 320676 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/320676
Apparatus for sending message via cable between programs and performing automatic operation in response to sent message Oct 10, 1994 Issued
Array ( [id] => 3504000 [patent_doc_number] => 05561824 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-01 [patent_title] => 'Storage management of data for ensuring communication of minimal length data' [patent_app_type] => 1 [patent_app_number] => 8/322441 [patent_app_country] => US [patent_app_date] => 1994-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3063 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/561/05561824.pdf [firstpage_image] =>[orig_patent_app_number] => 322441 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/322441
Storage management of data for ensuring communication of minimal length data Oct 3, 1994 Issued
Array ( [id] => 3540089 [patent_doc_number] => 05542058 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-30 [patent_title] => 'Pipelined computer with operand context queue to simplify context-dependent execution flow' [patent_app_type] => 1 [patent_app_number] => 8/317427 [patent_app_country] => US [patent_app_date] => 1994-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 21 [patent_no_of_words] => 34308 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/542/05542058.pdf [firstpage_image] =>[orig_patent_app_number] => 317427 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/317427
Pipelined computer with operand context queue to simplify context-dependent execution flow Oct 3, 1994 Issued
Array ( [id] => 3601657 [patent_doc_number] => 05551039 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-27 [patent_title] => 'Compiling a source code vector instruction by generating a subgrid loop for iteratively processing array elements by plural processing elements' [patent_app_type] => 1 [patent_app_number] => 8/315662 [patent_app_country] => US [patent_app_date] => 1994-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 7844 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/551/05551039.pdf [firstpage_image] =>[orig_patent_app_number] => 315662 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/315662
Compiling a source code vector instruction by generating a subgrid loop for iteratively processing array elements by plural processing elements Sep 29, 1994 Issued
Array ( [id] => 3601455 [patent_doc_number] => 05517639 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-14 [patent_title] => 'System for outputting execution time of industrial automated apparatus' [patent_app_type] => 1 [patent_app_number] => 8/311718 [patent_app_country] => US [patent_app_date] => 1994-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 22 [patent_no_of_words] => 6369 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/517/05517639.pdf [firstpage_image] =>[orig_patent_app_number] => 311718 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/311718
System for outputting execution time of industrial automated apparatus Sep 22, 1994 Issued
Array ( [id] => 3501460 [patent_doc_number] => 05471595 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-28 [patent_title] => 'Asynchronous interrupt inhibit method and apparatus for avoiding interrupt of an inseparable operation' [patent_app_type] => 1 [patent_app_number] => 8/307050 [patent_app_country] => US [patent_app_date] => 1994-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2667 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/471/05471595.pdf [firstpage_image] =>[orig_patent_app_number] => 307050 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/307050
Asynchronous interrupt inhibit method and apparatus for avoiding interrupt of an inseparable operation Sep 15, 1994 Issued
Array ( [id] => 3849686 [patent_doc_number] => 05761467 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-02 [patent_title] => 'System for committing execution results when branch conditions coincide with predetermined commit conditions specified in the instruction field' [patent_app_type] => 1 [patent_app_number] => 8/304441 [patent_app_country] => US [patent_app_date] => 1994-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 29 [patent_no_of_words] => 16069 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/761/05761467.pdf [firstpage_image] =>[orig_patent_app_number] => 304441 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/304441
System for committing execution results when branch conditions coincide with predetermined commit conditions specified in the instruction field Sep 11, 1994 Issued
Array ( [id] => 3612524 [patent_doc_number] => 05559999 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-24 [patent_title] => 'MPEG decoding system including tag list for associating presentation time stamps with encoded data units' [patent_app_type] => 1 [patent_app_number] => 8/303444 [patent_app_country] => US [patent_app_date] => 1994-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 4379 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/559/05559999.pdf [firstpage_image] =>[orig_patent_app_number] => 303444 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/303444
MPEG decoding system including tag list for associating presentation time stamps with encoded data units Sep 8, 1994 Issued
08/303338 METHOD AND APPARATUS FOR AUTOMATICALLY CONFIGURING AN INTERFACE Sep 8, 1994 Abandoned
Array ( [id] => 3560132 [patent_doc_number] => 05519435 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-21 [patent_title] => 'Multi-user, on-demand video storage and retrieval system including video signature computation for preventing excessive instantaneous server data rate' [patent_app_type] => 1 [patent_app_number] => 8/299829 [patent_app_country] => US [patent_app_date] => 1994-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 4075 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/519/05519435.pdf [firstpage_image] =>[orig_patent_app_number] => 299829 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/299829
Multi-user, on-demand video storage and retrieval system including video signature computation for preventing excessive instantaneous server data rate Aug 31, 1994 Issued
Array ( [id] => 3730487 [patent_doc_number] => 05617549 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-01 [patent_title] => 'System and method for selecting and buffering even and odd instructions for simultaneous execution in a computer' [patent_app_type] => 1 [patent_app_number] => 8/296989 [patent_app_country] => US [patent_app_date] => 1994-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6789 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/617/05617549.pdf [firstpage_image] =>[orig_patent_app_number] => 296989 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/296989
System and method for selecting and buffering even and odd instructions for simultaneous execution in a computer Aug 25, 1994 Issued
08/288525 APPARATUS AND METHOD FOR CONTROLLING THE ROTATIONAL SPEED OF A DISK IN A DATA STORAGE SYSTEM Aug 9, 1994 Abandoned
Array ( [id] => 3874910 [patent_doc_number] => RE035794 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-12 [patent_title] => 'System for reducing delay for execution subsequent to correctly predicted branch instruction using fetch information stored with each block of instructions in cache' [patent_app_type] => 2 [patent_app_number] => 8/285520 [patent_app_country] => US [patent_app_date] => 1994-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4066 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 17 [patent_words_short_claim] => 328 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/035/RE035794.pdf [firstpage_image] =>[orig_patent_app_number] => 285520 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/285520
System for reducing delay for execution subsequent to correctly predicted branch instruction using fetch information stored with each block of instructions in cache Aug 3, 1994 Issued
Array ( [id] => 4403521 [patent_doc_number] => 06263374 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'Apparatus for coupling a bus-based architecture to a switch network' [patent_app_type] => 1 [patent_app_number] => 8/286107 [patent_app_country] => US [patent_app_date] => 1994-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 21210 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/263/06263374.pdf [firstpage_image] =>[orig_patent_app_number] => 286107 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/286107
Apparatus for coupling a bus-based architecture to a switch network Aug 3, 1994 Issued
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