| Application number | Title of the application | Filing Date | Status |
|---|
Array
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Array
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[patent_issue_date] => 1996-07-09
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[firstpage_image] =>[orig_patent_app_number] => 270342
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Array
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[patent_doc_number] => 05485624
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-01-16
[patent_title] => 'Co-processor monitoring address generated by host processor to obtain DMA parameters in the unused portion of instructions'
[patent_app_type] => 1
[patent_app_number] => 8/269970
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Array
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[patent_doc_number] => 05548784
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-08-20
[patent_title] => 'Automatic disk change detection without causing head movement by step pulses'
[patent_app_type] => 1
[patent_app_number] => 8/263173
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[patent_app_date] => 1994-06-21
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[firstpage_image] =>[orig_patent_app_number] => 263173
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/263173 | Automatic disk change detection without causing head movement by step pulses | Jun 20, 1994 | Issued |
Array
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[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-07-16
[patent_title] => 'Method of computer conferencing by intercepting commands issued by application programs and redirecting to all stations for execution'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/259365 | Method of computer conferencing by intercepting commands issued by application programs and redirecting to all stations for execution | Jun 13, 1994 | Issued |
Array
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[patent_kind] => NA
[patent_issue_date] => 1996-02-06
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/255811 | System of dedicated elementary data processing machines organized in multiple levels and selectively activated to process incoming events | Jun 6, 1994 | Issued |
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[patent_issue_date] => 1996-08-20
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[firstpage_image] =>[orig_patent_app_number] => 249046
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/249046 | Data processing system with duplex common memory having physical and logical path disconnection upon failure | May 23, 1994 | Issued |
Array
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[patent_issue_date] => 1996-02-20
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[patent_app_type] => 1
[patent_app_number] => 8/245201
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[pdf_file] => patents/05/493/05493672.pdf
[firstpage_image] =>[orig_patent_app_number] => 245201
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/245201 | Concurrent simulation of host system at instruction level and input/output system at logic level with two-way communication deadlock resolution | May 15, 1994 | Issued |
Array
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[patent_issue_date] => 1996-06-25
[patent_title] => 'Superscalar processor with plural pipelined execution units each unit selectively having both normal and debug modes'
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[patent_issue_date] => 1996-08-13
[patent_title] => 'System for limiting change in bus clock frequency to duration of I/O operation upon completion signal'
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Array
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[patent_issue_date] => 1996-11-12
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Array
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Array
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| 08/228322 | METHOD AND SYSTEM FOR PROCESSING A BRANCH INSTRUCTION IN A PROCESSING SYSTEM | Apr 14, 1994 | Abandoned |
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