Search

Kenneth S. Kim

Examiner (ID: 328)

Most Active Art Unit
2111
Art Unit(s)
2783, 2315, 2181, 2183, 2784, 2111, 1107, 2302, 2185
Total Applications
1565
Issued Applications
1268
Pending Applications
37
Abandoned Applications
262

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3600434 [patent_doc_number] => 05497496 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-05 [patent_title] => 'Superscalar processor controlling fetching of instructions based upon number of empty instructions registers detected for each cycle' [patent_app_type] => 1 [patent_app_number] => 8/281128 [patent_app_country] => US [patent_app_date] => 1994-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5922 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/497/05497496.pdf [firstpage_image] =>[orig_patent_app_number] => 281128 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/281128
Superscalar processor controlling fetching of instructions based upon number of empty instructions registers detected for each cycle Jul 27, 1994 Issued
Array ( [id] => 3626111 [patent_doc_number] => 05535346 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-09 [patent_title] => 'Data processor with future file with parallel update and method of operation' [patent_app_type] => 1 [patent_app_number] => 8/270342 [patent_app_country] => US [patent_app_date] => 1994-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 5663 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/535/05535346.pdf [firstpage_image] =>[orig_patent_app_number] => 270342 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/270342
Data processor with future file with parallel update and method of operation Jul 4, 1994 Issued
Array ( [id] => 3579975 [patent_doc_number] => 05485624 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-16 [patent_title] => 'Co-processor monitoring address generated by host processor to obtain DMA parameters in the unused portion of instructions' [patent_app_type] => 1 [patent_app_number] => 8/269970 [patent_app_country] => US [patent_app_date] => 1994-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3297 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/485/05485624.pdf [firstpage_image] =>[orig_patent_app_number] => 269970 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/269970
Co-processor monitoring address generated by host processor to obtain DMA parameters in the unused portion of instructions Jun 30, 1994 Issued
Array ( [id] => 3563064 [patent_doc_number] => 05548784 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-20 [patent_title] => 'Automatic disk change detection without causing head movement by step pulses' [patent_app_type] => 1 [patent_app_number] => 8/263173 [patent_app_country] => US [patent_app_date] => 1994-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 11388 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/548/05548784.pdf [firstpage_image] =>[orig_patent_app_number] => 263173 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/263173
Automatic disk change detection without causing head movement by step pulses Jun 20, 1994 Issued
Array ( [id] => 3505265 [patent_doc_number] => 05537548 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-16 [patent_title] => 'Method of computer conferencing by intercepting commands issued by application programs and redirecting to all stations for execution' [patent_app_type] => 1 [patent_app_number] => 8/259365 [patent_app_country] => US [patent_app_date] => 1994-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 4088 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/537/05537548.pdf [firstpage_image] =>[orig_patent_app_number] => 259365 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/259365
Method of computer conferencing by intercepting commands issued by application programs and redirecting to all stations for execution Jun 13, 1994 Issued
Array ( [id] => 3532949 [patent_doc_number] => 05490273 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-06 [patent_title] => 'System of dedicated elementary data processing machines organized in multiple levels and selectively activated to process incoming events' [patent_app_type] => 1 [patent_app_number] => 8/255811 [patent_app_country] => US [patent_app_date] => 1994-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3457 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 290 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/490/05490273.pdf [firstpage_image] =>[orig_patent_app_number] => 255811 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/255811
System of dedicated elementary data processing machines organized in multiple levels and selectively activated to process incoming events Jun 6, 1994 Issued
Array ( [id] => 3562371 [patent_doc_number] => 05548743 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-20 [patent_title] => 'Data processing system with duplex common memory having physical and logical path disconnection upon failure' [patent_app_type] => 1 [patent_app_number] => 8/249046 [patent_app_country] => US [patent_app_date] => 1994-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 7115 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/548/05548743.pdf [firstpage_image] =>[orig_patent_app_number] => 249046 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/249046
Data processing system with duplex common memory having physical and logical path disconnection upon failure May 23, 1994 Issued
Array ( [id] => 3564666 [patent_doc_number] => 05493672 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-20 [patent_title] => 'Concurrent simulation of host system at instruction level and input/output system at logic level with two-way communication deadlock resolution' [patent_app_type] => 1 [patent_app_number] => 8/245201 [patent_app_country] => US [patent_app_date] => 1994-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5614 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/493/05493672.pdf [firstpage_image] =>[orig_patent_app_number] => 245201 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/245201
Concurrent simulation of host system at instruction level and input/output system at logic level with two-way communication deadlock resolution May 15, 1994 Issued
Array ( [id] => 3531792 [patent_doc_number] => 05530804 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-25 [patent_title] => 'Superscalar processor with plural pipelined execution units each unit selectively having both normal and debug modes' [patent_app_type] => 1 [patent_app_number] => 8/242767 [patent_app_country] => US [patent_app_date] => 1994-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 10543 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/530/05530804.pdf [firstpage_image] =>[orig_patent_app_number] => 242767 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/242767
Superscalar processor with plural pipelined execution units each unit selectively having both normal and debug modes May 15, 1994 Issued
Array ( [id] => 3561425 [patent_doc_number] => 05546567 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-13 [patent_title] => 'System for limiting change in bus clock frequency to duration of I/O operation upon completion signal' [patent_app_type] => 1 [patent_app_number] => 8/242073 [patent_app_country] => US [patent_app_date] => 1994-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4371 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/546/05546567.pdf [firstpage_image] =>[orig_patent_app_number] => 242073 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/242073
System for limiting change in bus clock frequency to duration of I/O operation upon completion signal May 12, 1994 Issued
Array ( [id] => 3566939 [patent_doc_number] => 05574928 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-12 [patent_title] => 'Mixed integer/floating point processor core for a superscalar microprocessor with a plurality of operand buses for transferring operand segments' [patent_app_type] => 1 [patent_app_number] => 8/233563 [patent_app_country] => US [patent_app_date] => 1994-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 19 [patent_no_of_words] => 7995 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 326 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/574/05574928.pdf [firstpage_image] =>[orig_patent_app_number] => 233563 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/233563
Mixed integer/floating point processor core for a superscalar microprocessor with a plurality of operand buses for transferring operand segments Apr 25, 1994 Issued
Array ( [id] => 3590144 [patent_doc_number] => 05491790 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-13 [patent_title] => 'Power-on sequencing apparatus for initializing and testing a system processing unit' [patent_app_type] => 1 [patent_app_number] => 8/231856 [patent_app_country] => US [patent_app_date] => 1994-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 7437 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 357 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/491/05491790.pdf [firstpage_image] =>[orig_patent_app_number] => 231856 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/231856
Power-on sequencing apparatus for initializing and testing a system processing unit Apr 21, 1994 Issued
Array ( [id] => 3604467 [patent_doc_number] => 05521972 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-28 [patent_title] => 'Communications system reconfigurable with reduced network configuration data' [patent_app_type] => 1 [patent_app_number] => 8/230227 [patent_app_country] => US [patent_app_date] => 1994-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 21 [patent_no_of_words] => 5100 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/521/05521972.pdf [firstpage_image] =>[orig_patent_app_number] => 230227 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/230227
Communications system reconfigurable with reduced network configuration data Apr 19, 1994 Issued
Array ( [id] => 3454810 [patent_doc_number] => 05467470 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-14 [patent_title] => 'Computer able to determine whether or not a display is connected to it, in accordance with the status data stored in a register, and method of detecting whether or not a display is connected to a computer' [patent_app_type] => 1 [patent_app_number] => 8/229810 [patent_app_country] => US [patent_app_date] => 1994-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 5432 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/467/05467470.pdf [firstpage_image] =>[orig_patent_app_number] => 229810 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/229810
Computer able to determine whether or not a display is connected to it, in accordance with the status data stored in a register, and method of detecting whether or not a display is connected to a computer Apr 18, 1994 Issued
08/228322 METHOD AND SYSTEM FOR PROCESSING A BRANCH INSTRUCTION IN A PROCESSING SYSTEM Apr 14, 1994 Abandoned
Array ( [id] => 3877758 [patent_doc_number] => 05793947 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-11 [patent_title] => 'Programmable controller for synchronously tracing the execution of operation blocks and SFC program execution method using the programmable controller' [patent_app_type] => 1 [patent_app_number] => 8/223101 [patent_app_country] => US [patent_app_date] => 1994-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 21 [patent_no_of_words] => 5721 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/793/05793947.pdf [firstpage_image] =>[orig_patent_app_number] => 223101 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/223101
Programmable controller for synchronously tracing the execution of operation blocks and SFC program execution method using the programmable controller Apr 3, 1994 Issued
Array ( [id] => 3458714 [patent_doc_number] => 05421028 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-30 [patent_title] => 'Processing commands and data in a common pipeline path in a high-speed computer graphics system' [patent_app_type] => 1 [patent_app_number] => 8/221271 [patent_app_country] => US [patent_app_date] => 1994-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 4013 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/421/05421028.pdf [firstpage_image] =>[orig_patent_app_number] => 221271 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/221271
Processing commands and data in a common pipeline path in a high-speed computer graphics system Mar 30, 1994 Issued
Array ( [id] => 3568965 [patent_doc_number] => 05502816 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-26 [patent_title] => 'Method of routing a request for a virtual circuit based on information from concurrent requests' [patent_app_type] => 1 [patent_app_number] => 8/218390 [patent_app_country] => US [patent_app_date] => 1994-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2736 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/502/05502816.pdf [firstpage_image] =>[orig_patent_app_number] => 218390 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/218390
Method of routing a request for a virtual circuit based on information from concurrent requests Mar 24, 1994 Issued
Array ( [id] => 3606161 [patent_doc_number] => 05522075 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-28 [patent_title] => 'Protection ring extension for computers having distinct virtual machine monitor and virtual machine address spaces' [patent_app_type] => 1 [patent_app_number] => 8/216509 [patent_app_country] => US [patent_app_date] => 1994-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 7603 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/522/05522075.pdf [firstpage_image] =>[orig_patent_app_number] => 216509 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/216509
Protection ring extension for computers having distinct virtual machine monitor and virtual machine address spaces Mar 21, 1994 Issued
Array ( [id] => 3507192 [patent_doc_number] => 05509123 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-16 [patent_title] => 'Distributed autonomous object architectures for network layer routing' [patent_app_type] => 1 [patent_app_number] => 8/216541 [patent_app_country] => US [patent_app_date] => 1994-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 26 [patent_no_of_words] => 15052 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/509/05509123.pdf [firstpage_image] =>[orig_patent_app_number] => 216541 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/216541
Distributed autonomous object architectures for network layer routing Mar 21, 1994 Issued
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