| Application number | Title of the application | Filing Date | Status |
|---|
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[patent_title] => 'Reconfigurable architecture for multi-protocol data communications having selection means and a plurality of register sets'
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[patent_app_number] => 8/201716
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Array
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[patent_doc_number] => 05553216
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[patent_kind] => NA
[patent_issue_date] => 1996-09-03
[patent_title] => 'Structured database system together with structure definition frame storing document body data'
[patent_app_type] => 1
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/202193 | Structured database system together with structure definition frame storing document body data | Feb 23, 1994 | Issued |
Array
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[id] => 3600869
[patent_doc_number] => 05553311
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-09-03
[patent_title] => 'Customer premise device for controlling data transmissions by storing a limited number of operation algorithms and receiving operation instructions from external sources'
[patent_app_type] => 1
[patent_app_number] => 8/197810
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/197810 | Customer premise device for controlling data transmissions by storing a limited number of operation algorithms and receiving operation instructions from external sources | Feb 16, 1994 | Issued |
| 08/198142 | INTELLIGENT NETWORK SERVICE MANAGEMENT PROCESSES AND DEVICES | Feb 16, 1994 | Abandoned |
Array
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[id] => 3537651
[patent_doc_number] => 05504903
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-04-02
[patent_title] => 'Self-progamming of on-chip program memory for microcontroller at clock start-up'
[patent_app_type] => 1
[patent_app_number] => 8/192958
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Array
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[id] => 3532837
[patent_doc_number] => 05490266
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-02-06
[patent_title] => 'Process oriented logic simulation having stability checking'
[patent_app_type] => 1
[patent_app_number] => 8/192185
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| 08/189269 | SYNCHRONIZING PARALLEL PROCESSORS USING BARRIERS EXTENDING OVER SPECIFIC MULTIPLE-INSTRUCTION REGIONS IN EACH INSTRUCTION STREAM | Jan 30, 1994 | Abandoned |
| 08/188974 | INSTRUCTION ACCELERATOR | Jan 30, 1994 | Abandoned |
Array
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Array
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[patent_kind] => NA
[patent_issue_date] => 1996-03-26
[patent_title] => 'System and method for obtaining parallel existing instructions in a particular data processing configuration by compounding instructions'
[patent_app_type] => 1
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[firstpage_image] =>[orig_patent_app_number] => 186221
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Array
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[id] => 3500900
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[patent_kind] => NA
[patent_issue_date] => 1995-12-12
[patent_title] => 'Cache store of instruction pairs with tags to indicate parallel execution'
[patent_app_type] => 1
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Array
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Array
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[patent_issue_date] => 2000-03-07
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/184417 | Storage of user defined type file data in corresponding select physical format | Jan 20, 1994 | Issued |
| 08/184891 | GENERAL PURPOSE COMPOUNDING TECHNIQUE FOR INSTRUCTION LEVEL PARALLEL PROCESSORS | Jan 20, 1994 | Abandoned |
| 08/183478 | ALTERNATE DISPATCH VARIABLE PROCESS AND ARRANGEMENT FOR RUN-TIME MESSAGE REDIRECTION AND ENABLEMENT OF SELECTED OBJECT ORIENTED METHODS | Jan 17, 1994 | Abandoned |
Array
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[patent_kind] => NA
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Array
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Array
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