Kenneth S. Kim

Array ( [id] => 4156790 [patent_doc_number] => 06122767 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'Method and apparatus for noise reduction of cyclic signal by selecting majority logic state of corresponding portions of plural cycles' [patent_app_type] => 1 [patent_app_number] => 8/156544 [patent_app_country] => US [patent_app_date] => 1993-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 26 [patent_no_of_words] => 11442 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/122/06122767.pdf [firstpage_image] =>[orig_patent_app_number] => 156544 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4162773 [patent_doc_number] => 06124866 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-26 [patent_title] => 'Multiprocessor system with unit processors assigned a plurality of non-contiguous regions' [patent_app_type] => 1 [patent_app_number] => 8/150548 [patent_app_country] => US [patent_app_date] => 1993-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 25 [patent_no_of_words] => 10323 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/124/06124866.pdf [firstpage_image] =>[orig_patent_app_number] => 150548 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3440800 [patent_doc_number] => 05463750 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-31 [patent_title] => 'Method and apparatus for translating virtual addresses in a data processing system having multiple instruction pipelines and separate TLB\'s' [patent_app_type] => 1 [patent_app_number] => 8/146818 [patent_app_country] => US [patent_app_date] => 1993-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3123 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 311 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/463/05463750.pdf [firstpage_image] =>[orig_patent_app_number] => 146818 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3426999 [patent_doc_number] => 05454089 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-26 [patent_title] => 'Branch look ahead adder for use in an instruction pipeline sequencer with multiple instruction decoding' [patent_app_type] => 1 [patent_app_number] => 8/141685 [patent_app_country] => US [patent_app_date] => 1993-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5248 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 321 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/454/05454089.pdf [firstpage_image] =>[orig_patent_app_number] => 141685 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3439203 [patent_doc_number] => 05455929 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-03 [patent_title] => 'Logic simulator employing hierarchical checkpointing' [patent_app_type] => 1 [patent_app_number] => 8/136520 [patent_app_country] => US [patent_app_date] => 1993-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 5259 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/455/05455929.pdf [firstpage_image] =>[orig_patent_app_number] => 136520 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3009643 [patent_doc_number] => 05363497 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-11-08 [patent_title] => 'System for removing section of memory from first system and allocating to second system in a manner indiscernable to both operating systems' [patent_app_type] => 1 [patent_app_number] => 8/128760 [patent_app_country] => US [patent_app_date] => 1993-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 84 [patent_figures_cnt] => 135 [patent_no_of_words] => 77695 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/363/05363497.pdf [firstpage_image] =>[orig_patent_app_number] => 128760 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3118388 [patent_doc_number] => 05448739 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-05 [patent_title] => 'Method of recording, playback and re-execution of application program call sequences and import and export of data in a digital computer system' [patent_app_type] => 1 [patent_app_number] => 8/126428 [patent_app_country] => US [patent_app_date] => 1993-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 9131 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/448/05448739.pdf [firstpage_image] =>[orig_patent_app_number] => 126428 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3420024 [patent_doc_number] => 05438664 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-01 [patent_title] => 'Method and apparatus for producing slips of variable length and having user-defined word names and associated word data thereon' [patent_app_type] => 1 [patent_app_number] => 8/126136 [patent_app_country] => US [patent_app_date] => 1993-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 34 [patent_no_of_words] => 8700 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 322 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/438/05438664.pdf [firstpage_image] =>[orig_patent_app_number] => 126136 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3457140 [patent_doc_number] => 05388264 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-07 [patent_title] => 'Object oriented framework system for routing, editing, and synchronizing MIDI multimedia information using graphically represented connection object' [patent_app_type] => 1 [patent_app_number] => 8/114640 [patent_app_country] => US [patent_app_date] => 1993-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 63 [patent_no_of_words] => 12226 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/388/05388264.pdf [firstpage_image] =>[orig_patent_app_number] => 114640 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3420152 [patent_doc_number] => 05438672 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-01 [patent_title] => 'Microcontroller emulator for plural device architecture configured by mode control data and operated under control code transmitted via same switching bus' [patent_app_type] => 1 [patent_app_number] => 8/113526 [patent_app_country] => US [patent_app_date] => 1993-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 3752 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/438/05438672.pdf [firstpage_image] =>[orig_patent_app_number] => 113526 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3526172 [patent_doc_number] => 05513321 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-30 [patent_title] => 'Multiprocessor system discharging data in networking apparatus in response to off-line information from receiver-side processor' [patent_app_type] => 1 [patent_app_number] => 8/110936 [patent_app_country] => US [patent_app_date] => 1993-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7457 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 434 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/513/05513321.pdf [firstpage_image] =>[orig_patent_app_number] => 110936 [rel_patent_id] =>[rel_patent_doc_number] =>)