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Kenneth S. Kim

Examiner (ID: 328)

Most Active Art Unit
2111
Art Unit(s)
2783, 2315, 2181, 2183, 2784, 2111, 1107, 2302, 2185
Total Applications
1565
Issued Applications
1268
Pending Applications
37
Abandoned Applications
262

Applications

Application numberTitle of the applicationFiling DateStatus
08/013982 SYSTEM AND METHOD FOR OBTAINING PARALLEL EXISTING INSTRUCTIONS IN A PARTICULAR DATA PROCESSING CONFIGURATION BY COMPOUNDING INSTRUCTIONS Feb 4, 1993 Abandoned
08/015272 GENERAL PURPOSE COMPOUNDING TECHNIQUE FOR INSTRUCTION LEVEL PARALLEL PROCESSORS Feb 4, 1993 Abandoned
08/003935 PATTERN EDITING INFORMATION PROCESSING APPATATUS Jan 20, 1993 Abandoned
Array ( [id] => 3024180 [patent_doc_number] => 05333297 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-07-26 [patent_title] => 'Multiprocessor system having multiple classes of instructions for purposes of mutual interruptibility' [patent_app_type] => 1 [patent_app_number] => 8/005928 [patent_app_country] => US [patent_app_date] => 1993-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 7056 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/333/05333297.pdf [firstpage_image] =>[orig_patent_app_number] => 005928 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/005928
Multiprocessor system having multiple classes of instructions for purposes of mutual interruptibility Jan 18, 1993 Issued
Array ( [id] => 3032646 [patent_doc_number] => 05303358 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-04-12 [patent_title] => 'Prefix instruction for modification of a subsequent instruction' [patent_app_type] => 1 [patent_app_number] => 8/004627 [patent_app_country] => US [patent_app_date] => 1993-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2661 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/303/05303358.pdf [firstpage_image] =>[orig_patent_app_number] => 004627 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/004627
Prefix instruction for modification of a subsequent instruction Jan 13, 1993 Issued
08/001479 COMPOUNDING PREPROCESSOR FOR CACHE Jan 6, 1993 Abandoned
Array ( [id] => 4162522 [patent_doc_number] => 06032244 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-29 [patent_title] => 'Multiple issue static speculative instruction scheduling with path tag and precise interrupt handling' [patent_app_type] => 1 [patent_app_number] => 8/000342 [patent_app_country] => US [patent_app_date] => 1993-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 7741 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/032/06032244.pdf [firstpage_image] =>[orig_patent_app_number] => 000342 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/000342
Multiple issue static speculative instruction scheduling with path tag and precise interrupt handling Jan 3, 1993 Issued
Array ( [id] => 3470195 [patent_doc_number] => 05473756 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-12-05 [patent_title] => 'FIFO buffer with full/empty detection by comparing respective registers in read and write circular shift registers' [patent_app_type] => 1 [patent_app_number] => 7/998942 [patent_app_country] => US [patent_app_date] => 1992-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5865 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/473/05473756.pdf [firstpage_image] =>[orig_patent_app_number] => 998942 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/998942
FIFO buffer with full/empty detection by comparing respective registers in read and write circular shift registers Dec 29, 1992 Issued
Array ( [id] => 3472108 [patent_doc_number] => 05442772 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-15 [patent_title] => 'Common breakpoint in virtual time logic simulation for parallel processors' [patent_app_type] => 1 [patent_app_number] => 7/993142 [patent_app_country] => US [patent_app_date] => 1992-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6548 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/442/05442772.pdf [firstpage_image] =>[orig_patent_app_number] => 993142 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/993142
Common breakpoint in virtual time logic simulation for parallel processors Dec 17, 1992 Issued
07/992944 FAIL-FAST, FAIL-FUNCTIONAL, FAULT-TOLERANT MULTIPROCESSOR SYSTEM Dec 16, 1992 Abandoned
Array ( [id] => 3502716 [patent_doc_number] => 05440714 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-08 [patent_title] => 'Method and system configuration for simplifying the decoding system for access to an register file with overlapping windows' [patent_app_type] => 1 [patent_app_number] => 7/990641 [patent_app_country] => US [patent_app_date] => 1992-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 4672 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 353 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/440/05440714.pdf [firstpage_image] =>[orig_patent_app_number] => 990641 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/990641
Method and system configuration for simplifying the decoding system for access to an register file with overlapping windows Dec 13, 1992 Issued
Array ( [id] => 3042484 [patent_doc_number] => 05317750 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-05-31 [patent_title] => 'Microcontroller peripheral expansion bus for access to internal special function registers' [patent_app_type] => 1 [patent_app_number] => 7/984280 [patent_app_country] => US [patent_app_date] => 1992-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2770 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 336 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/317/05317750.pdf [firstpage_image] =>[orig_patent_app_number] => 984280 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/984280
Microcontroller peripheral expansion bus for access to internal special function registers Nov 30, 1992 Issued
Array ( [id] => 3497690 [patent_doc_number] => 05426768 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-06-20 [patent_title] => 'Logic simulation with efficient deadlock avoidance by selectively suspending event data fetch based on element information' [patent_app_type] => 1 [patent_app_number] => 7/975841 [patent_app_country] => US [patent_app_date] => 1992-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5497 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/426/05426768.pdf [firstpage_image] =>[orig_patent_app_number] => 975841 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/975841
Logic simulation with efficient deadlock avoidance by selectively suspending event data fetch based on element information Nov 12, 1992 Issued
07/975245 A SYSTEM AND METHOD FOR SIMULATING A CONTGUOUS ADDRESSABLE DATA SPACE FOR MAPPING ON DEMAND A DESIRED PAGE OF A DATA OBJECT UPON FIRST REFERENCE OF THE PAGE Nov 11, 1992 Abandoned
Array ( [id] => 3015905 [patent_doc_number] => 05371881 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-12-06 [patent_title] => 'Universal timing controller for video tape recorder servo system of different formats using time multiplexed switching network' [patent_app_type] => 1 [patent_app_number] => 7/973536 [patent_app_country] => US [patent_app_date] => 1992-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 6569 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 286 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/371/05371881.pdf [firstpage_image] =>[orig_patent_app_number] => 973536 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/973536
Universal timing controller for video tape recorder servo system of different formats using time multiplexed switching network Nov 8, 1992 Issued
07/967565 VECTOR DATA PROCESSING APPARATUS WITH IMMEDIATE RANK SLOT ASSIGNMENT FOR VECTOR LOAD INSTRUCTION Oct 27, 1992 Abandoned
Array ( [id] => 3426971 [patent_doc_number] => 05454087 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-26 [patent_title] => 'Branching system for return from subroutine using target address in return buffer accessed based on branch type information in BHT' [patent_app_type] => 1 [patent_app_number] => 7/965441 [patent_app_country] => US [patent_app_date] => 1992-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 6498 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 308 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/454/05454087.pdf [firstpage_image] =>[orig_patent_app_number] => 965441 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/965441
Branching system for return from subroutine using target address in return buffer accessed based on branch type information in BHT Oct 22, 1992 Issued
Array ( [id] => 3590229 [patent_doc_number] => 05491796 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-13 [patent_title] => 'Apparatus for remotely managing diverse information network resources' [patent_app_type] => 1 [patent_app_number] => 7/965350 [patent_app_country] => US [patent_app_date] => 1992-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 25529 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 391 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/491/05491796.pdf [firstpage_image] =>[orig_patent_app_number] => 965350 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/965350
Apparatus for remotely managing diverse information network resources Oct 22, 1992 Issued
Array ( [id] => 2977807 [patent_doc_number] => 05274835 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-12-28 [patent_title] => 'Merge device using FIFO buffers' [patent_app_type] => 1 [patent_app_number] => 7/958465 [patent_app_country] => US [patent_app_date] => 1992-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 5885 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/274/05274835.pdf [firstpage_image] =>[orig_patent_app_number] => 958465 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/958465
Merge device using FIFO buffers Oct 7, 1992 Issued
07/957344 SYSTEM AND METHOD FOR SELECTING AND BUFFERING MULTIPLE INSTRUCTIONS FOR SIMULTANEOUS EXECUTION IN A COMPUTER Oct 5, 1992 Abandoned
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