| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 8823783
[patent_doc_number] => 20130124828
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-05-16
[patent_title] => 'REDUCING HARDWARE COSTS FOR SUPPORTING MISS LOOKAHEAD'
[patent_app_type] => utility
[patent_app_number] => 13/293724
[patent_app_country] => US
[patent_app_date] => 2011-11-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5695
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13293724
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/293724 | Prefetching load data in lookahead mode and invalidating architectural registers instead of writing results for retiring instructions | Nov 9, 2011 | Issued |
Array
(
[id] => 7809066
[patent_doc_number] => 20120060020
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-03-08
[patent_title] => 'VECTOR INDEX INSTRUCTION FOR PROCESSING VECTORS'
[patent_app_type] => utility
[patent_app_number] => 13/291931
[patent_app_country] => US
[patent_app_date] => 2011-11-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 25
[patent_no_of_words] => 37100
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0060/20120060020.pdf
[firstpage_image] =>[orig_patent_app_number] => 13291931
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/291931 | Vector index instruction for generating a result vector with incremental values based on a start value and an increment value | Nov 7, 2011 | Issued |
Array
(
[id] => 8816535
[patent_doc_number] => 20130117580
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-05-09
[patent_title] => 'COMPACT UNIVERSAL WIRELESS ADAPTER'
[patent_app_type] => utility
[patent_app_number] => 13/290445
[patent_app_country] => US
[patent_app_date] => 2011-11-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 3890
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13290445
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/290445 | COMPACT UNIVERSAL WIRELESS ADAPTER | Nov 6, 2011 | Abandoned |
Array
(
[id] => 8816490
[patent_doc_number] => 20130117535
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-05-09
[patent_title] => 'Selective Writing of Branch Target Buffer'
[patent_app_type] => utility
[patent_app_number] => 13/289007
[patent_app_country] => US
[patent_app_date] => 2011-11-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 6113
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13289007
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/289007 | Selective writing of branch target buffer when number of instructions in cache line containing branch instruction is less than threshold | Nov 3, 2011 | Issued |
Array
(
[id] => 9967879
[patent_doc_number] => 09015513
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-04-21
[patent_title] => 'Receiving application specific individual battery adjusted battery use profile data upon loading of work application for managing remaining power of a mobile device'
[patent_app_type] => utility
[patent_app_number] => 13/288476
[patent_app_country] => US
[patent_app_date] => 2011-11-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 6145
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 228
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13288476
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/288476 | Receiving application specific individual battery adjusted battery use profile data upon loading of work application for managing remaining power of a mobile device | Nov 2, 2011 | Issued |
Array
(
[id] => 10867126
[patent_doc_number] => 08892851
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-11-18
[patent_title] => 'Changing opcode of subsequent instruction when same destination address is not used as source address by intervening instructions'
[patent_app_type] => utility
[patent_app_number] => 13/287412
[patent_app_country] => US
[patent_app_date] => 2011-11-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 12690
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13287412
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/287412 | Changing opcode of subsequent instruction when same destination address is not used as source address by intervening instructions | Nov 1, 2011 | Issued |
Array
(
[id] => 9961227
[patent_doc_number] => 09009451
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-04-14
[patent_title] => 'Instruction type issue throttling upon reaching threshold by adjusting counter increment amount for issued cycle and decrement amount for not issued cycle'
[patent_app_type] => utility
[patent_app_number] => 13/285361
[patent_app_country] => US
[patent_app_date] => 2011-10-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 7352
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 152
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13285361
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/285361 | Instruction type issue throttling upon reaching threshold by adjusting counter increment amount for issued cycle and decrement amount for not issued cycle | Oct 30, 2011 | Issued |
Array
(
[id] => 10854142
[patent_doc_number] => 08880852
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-11-04
[patent_title] => 'Detecting logically non-significant operation based on opcode and operand and setting flag to decode address specified in subsequent instruction as different address'
[patent_app_type] => utility
[patent_app_number] => 13/281958
[patent_app_country] => US
[patent_app_date] => 2011-10-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 9
[patent_no_of_words] => 10985
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13281958
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/281958 | Detecting logically non-significant operation based on opcode and operand and setting flag to decode address specified in subsequent instruction as different address | Oct 25, 2011 | Issued |
Array
(
[id] => 8781950
[patent_doc_number] => 20130103925
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-04-25
[patent_title] => 'Method and System for Folding a SIMD Array'
[patent_app_type] => utility
[patent_app_number] => 13/281149
[patent_app_country] => US
[patent_app_date] => 2011-10-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 5827
[patent_no_of_claims] => 41
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13281149
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/281149 | Folded SIMD array organized in groups (PEGs) of respective array segments, control signal distribution logic, and local memory | Oct 24, 2011 | Issued |
Array
(
[id] => 10124186
[patent_doc_number] => 09158545
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-10-13
[patent_title] => 'Looking ahead bytecode stream to generate and update prediction information in branch target buffer for branching from the end of preceding bytecode handler to the beginning of current bytecode handler'
[patent_app_type] => utility
[patent_app_number] => 13/276083
[patent_app_country] => US
[patent_app_date] => 2011-10-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4114
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 181
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13276083
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/276083 | Looking ahead bytecode stream to generate and update prediction information in branch target buffer for branching from the end of preceding bytecode handler to the beginning of current bytecode handler | Oct 17, 2011 | Issued |
Array
(
[id] => 7820072
[patent_doc_number] => 20120066692
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-03-15
[patent_title] => 'ITERATIVELY PROCESSING SEGMENTS BY CONCURRENTLY TRANSMITTING TO, PROCESSING BY, AND RECEIVING FROM PARTNERED PROCESS'
[patent_app_type] => utility
[patent_app_number] => 13/269619
[patent_app_country] => US
[patent_app_date] => 2011-10-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 19173
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0066/20120066692.pdf
[firstpage_image] =>[orig_patent_app_number] => 13269619
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/269619 | Iterative process partner pairing scheme for global reduce operation | Oct 8, 2011 | Issued |
Array
(
[id] => 8735245
[patent_doc_number] => 20130080814
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-03-28
[patent_title] => 'COMPUTATIONAL CLUSTER POWER CONSUMPTION AND AVAILABILITY MANAGEMENT'
[patent_app_type] => utility
[patent_app_number] => 13/241614
[patent_app_country] => US
[patent_app_date] => 2011-09-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 8373
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13241614
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/241614 | Cluster computational capacity level switching based on demand prediction and stability constraint and power consumption management | Sep 22, 2011 | Issued |
Array
(
[id] => 8735242
[patent_doc_number] => 20130080811
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-03-28
[patent_title] => 'Low Power Input Device'
[patent_app_type] => utility
[patent_app_number] => 13/244020
[patent_app_country] => US
[patent_app_date] => 2011-09-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 7077
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13244020
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/244020 | Operating input device in low power mode with auxiliary sensor calibrated to main sensor | Sep 22, 2011 | Issued |
Array
(
[id] => 9765818
[patent_doc_number] => 08850167
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-09-30
[patent_title] => 'Loading/discarding acquired data for vector load instruction upon determination of prediction success of multiple preceding branch instructions'
[patent_app_type] => utility
[patent_app_number] => 13/240614
[patent_app_country] => US
[patent_app_date] => 2011-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 10322
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 412
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13240614
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/240614 | Loading/discarding acquired data for vector load instruction upon determination of prediction success of multiple preceding branch instructions | Sep 21, 2011 | Issued |
Array
(
[id] => 9629932
[patent_doc_number] => 08799626
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-08-05
[patent_title] => 'Prioritized assignment of sub-range registers of circularly addressable extended register file to loop variables in RISC processor'
[patent_app_type] => utility
[patent_app_number] => 13/229078
[patent_app_country] => US
[patent_app_date] => 2011-09-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 3027
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 474
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13229078
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/229078 | Prioritized assignment of sub-range registers of circularly addressable extended register file to loop variables in RISC processor | Sep 8, 2011 | Issued |
Array
(
[id] => 8709916
[patent_doc_number] => 20130067205
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-03-14
[patent_title] => 'INSTRUCTION PACKET INCLUDING MULTIPLE INSTRUCTIONS HAVING A COMMON DESTINATION'
[patent_app_type] => utility
[patent_app_number] => 13/228601
[patent_app_country] => US
[patent_app_date] => 2011-09-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 6019
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13228601
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/228601 | Executing instruction packet with multiple instructions with same destination by performing logical operation on results of instructions and storing the result to the destination | Sep 8, 2011 | Issued |
Array
(
[id] => 10046490
[patent_doc_number] => 09086887
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-07-21
[patent_title] => 'Virtual register mode by designation of dedicated register as destination operand with switch connecting execution result feedback path and turning clock off to register file'
[patent_app_type] => utility
[patent_app_number] => 13/228978
[patent_app_country] => US
[patent_app_date] => 2011-09-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4306
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 306
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13228978
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/228978 | Virtual register mode by designation of dedicated register as destination operand with switch connecting execution result feedback path and turning clock off to register file | Sep 8, 2011 | Issued |
Array
(
[id] => 8491413
[patent_doc_number] => 20120290820
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-11-15
[patent_title] => 'SUPPRESSION OF CONTROL TRANSFER INSTRUCTIONS ON INCORRECT SPECULATIVE EXECUTION PATHS'
[patent_app_type] => utility
[patent_app_number] => 13/228329
[patent_app_country] => US
[patent_app_date] => 2011-09-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 11598
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13228329
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/228329 | Suppressing branch prediction information update by branch instructions in incorrect speculative execution path | Sep 7, 2011 | Issued |
Array
(
[id] => 8491410
[patent_doc_number] => 20120290817
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-11-15
[patent_title] => 'BRANCH TARGET STORAGE AND RETRIEVAL IN AN OUT-OF-ORDER PROCESSOR'
[patent_app_type] => utility
[patent_app_number] => 13/228347
[patent_app_country] => US
[patent_app_date] => 2011-09-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 11305
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13228347
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/228347 | Associating tag to branch instruction to access array storing predicted target addresses for page crossing targets for comparison with resolved address at execution stage | Sep 7, 2011 | Issued |
Array
(
[id] => 9707324
[patent_doc_number] => 08832417
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-09-09
[patent_title] => 'Program flow control for multiple divergent SIMD threads using a minimum resume counter'
[patent_app_type] => utility
[patent_app_number] => 13/227274
[patent_app_country] => US
[patent_app_date] => 2011-09-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 30
[patent_figures_cnt] => 36
[patent_no_of_words] => 27093
[patent_no_of_claims] => 40
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 161
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13227274
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/227274 | Program flow control for multiple divergent SIMD threads using a minimum resume counter | Sep 6, 2011 | Issued |