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Kenneth S. Kim

Examiner (ID: 328)

Most Active Art Unit
2111
Art Unit(s)
2783, 2315, 2181, 2183, 2784, 2111, 1107, 2302, 2185
Total Applications
1565
Issued Applications
1268
Pending Applications
37
Abandoned Applications
262

Applications

Application numberTitle of the applicationFiling DateStatus
07/955845 METHOD FOR IMPROVING SCSI OPERATIONS BY ACTIVELY PATCHING SCSI PROCESSOR INSTRUCTIONS Oct 1, 1992 Abandoned
07/954547 CONCURRENT FAULT SIMULATION OF CIRCUITS WITH BOTH LOGIC ELEMENTS AND FUNCTIONAL CIRCUITS Sep 29, 1992 Abandoned
Array ( [id] => 3093710 [patent_doc_number] => 05321821 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-06-14 [patent_title] => 'System for processing parameters in instructions of different format to execute the instructions using same microinstructions' [patent_app_type] => 1 [patent_app_number] => 7/954096 [patent_app_country] => US [patent_app_date] => 1992-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 36 [patent_no_of_words] => 13602 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/321/05321821.pdf [firstpage_image] =>[orig_patent_app_number] => 954096 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/954096
System for processing parameters in instructions of different format to execute the instructions using same microinstructions Sep 28, 1992 Issued
Array ( [id] => 3015725 [patent_doc_number] => 05371871 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-12-06 [patent_title] => 'System for swapping in and out of system memory TSR programs by trapping interrupt calls for TSR and simulating system interrupt' [patent_app_type] => 1 [patent_app_number] => 7/951846 [patent_app_country] => US [patent_app_date] => 1992-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 4320 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 400 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/371/05371871.pdf [firstpage_image] =>[orig_patent_app_number] => 951846 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/951846
System for swapping in and out of system memory TSR programs by trapping interrupt calls for TSR and simulating system interrupt Sep 27, 1992 Issued
07/947644 SLAVE APPARATUS FOR CONVERTING BETWEEN BUS-BASED INTERFACE AND PROTOCOL AND SWITCH-BASED INTERFACE AND PROTOCOL Sep 16, 1992 Abandoned
Array ( [id] => 2902264 [patent_doc_number] => 05239663 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-08-24 [patent_title] => 'Self-adapting and multifunctional process and structure for the automated evaluation of logical or arithmetic expressions, particularly for extended database consultation' [patent_app_type] => 1 [patent_app_number] => 7/930562 [patent_app_country] => US [patent_app_date] => 1992-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 25 [patent_no_of_words] => 23420 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 500 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/239/05239663.pdf [firstpage_image] =>[orig_patent_app_number] => 930562 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/930562
Self-adapting and multifunctional process and structure for the automated evaluation of logical or arithmetic expressions, particularly for extended database consultation Aug 13, 1992 Issued
07/927082 APPLICATION DISTRIBUTED EXECUTION APPARATUS AND METHOD Aug 6, 1992 Abandoned
07/924742 METHOD AND APPARATUS FOR EXECUTING FLOATING INSTRUCTIONS IN A PIPELINED PROCESSOR Aug 3, 1992 Abandoned
07/921612 SYSTEM AND METHOD FOR CONTROLLING A SYSTEM BUS IN A COMPUTER SYSTEM Aug 2, 1992 Abandoned
Array ( [id] => 3053194 [patent_doc_number] => 05377336 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-12-27 [patent_title] => 'Improved method to prefetch load instruction data' [patent_app_type] => 1 [patent_app_number] => 7/920947 [patent_app_country] => US [patent_app_date] => 1992-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 5978 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 317 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/377/05377336.pdf [firstpage_image] =>[orig_patent_app_number] => 920947 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/920947
Improved method to prefetch load instruction data Jul 27, 1992 Issued
Array ( [id] => 2980039 [patent_doc_number] => 05202967 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-04-13 [patent_title] => 'Data processing apparatus for performing parallel decoding and parallel execution of a variable word length instruction' [patent_app_type] => 1 [patent_app_number] => 7/916804 [patent_app_country] => US [patent_app_date] => 1992-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 4114 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/202/05202967.pdf [firstpage_image] =>[orig_patent_app_number] => 916804 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/916804
Data processing apparatus for performing parallel decoding and parallel execution of a variable word length instruction Jul 19, 1992 Issued
07/909545 PIPELINED COMPUTER WITH OPERAND CONTEXT QUEUE TO SIMPLIFY CONTEXT-DEPENDENT EXECUTION FLOW Jul 5, 1992 Abandoned
07/909544 PIPELINE COMPUTER WITH SYNCHRONIZATION COUNTER TO ENFORCE MEMORY ORDERING FOR INSTRUCTIONS IN WHICH SYNCHRONIZATION POINTS ARE NOT PREDTERMINED AT INSTRUCTION DECODE Jul 5, 1992 Abandoned
07/906631 3-1 ARITHMETIC LOGIC UNIT Jun 29, 1992 Abandoned
Array ( [id] => 3949868 [patent_doc_number] => 05940504 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-17 [patent_title] => 'Licensing management system and method in which datagrams including an address of a licensee and indicative of use of a licensed product are sent from the licensee\'s site' [patent_app_type] => 1 [patent_app_number] => 7/907934 [patent_app_country] => US [patent_app_date] => 1992-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6506 [patent_no_of_claims] => 105 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/940/05940504.pdf [firstpage_image] =>[orig_patent_app_number] => 907934 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/907934
Licensing management system and method in which datagrams including an address of a licensee and indicative of use of a licensed product are sent from the licensee's site Jun 28, 1992 Issued
Array ( [id] => 3602950 [patent_doc_number] => 05488724 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-30 [patent_title] => 'Network controller with memory request and acknowledgement signals and a network adapter therewith' [patent_app_type] => 1 [patent_app_number] => 7/883748 [patent_app_country] => US [patent_app_date] => 1992-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 31 [patent_no_of_words] => 12178 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/488/05488724.pdf [firstpage_image] =>[orig_patent_app_number] => 883748 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/883748
Network controller with memory request and acknowledgement signals and a network adapter therewith May 14, 1992 Issued
07/880133 SYSTEM FOR HANDLING EXCEPTIONS OCCURRING DURING PARALLEL EXECUTION OF MICROINSTRUCTIONS May 5, 1992 Abandoned
07/874945 A SUPERSCALER PROCESSOR WITH INSTRUCTION FETCHING CONTROLLED IN EACH CYCLE IN RESPONSE TO THE NUMBER OF EMPTY INSTRUCTION REGISTERS Apr 28, 1992 Abandoned
Array ( [id] => 2990519 [patent_doc_number] => 05257394 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-10-26 [patent_title] => 'Logical expression processing pipeline using pushdown stacks for a vector computer' [patent_app_type] => 1 [patent_app_number] => 7/872147 [patent_app_country] => US [patent_app_date] => 1992-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 3654 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/257/05257394.pdf [firstpage_image] =>[orig_patent_app_number] => 872147 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/872147
Logical expression processing pipeline using pushdown stacks for a vector computer Apr 21, 1992 Issued
07/869826 METHOD AND APPARATUS FOR PRODUCING SLIPS OF VARIABLE LENGTH AND HAVING PRE-STORED WORD NAMES AND ASSOCIATED WORD DATA THEREON Apr 14, 1992 Abandoned
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