Search

Kenneth S. Kim

Examiner (ID: 328)

Most Active Art Unit
2111
Art Unit(s)
2783, 2315, 2181, 2183, 2784, 2111, 1107, 2302, 2185
Total Applications
1565
Issued Applications
1268
Pending Applications
37
Abandoned Applications
262

Applications

Application numberTitle of the applicationFiling DateStatus
07/863250 ASYNCHRONOUS INTERRUPT INHIBIT METHOD AND APPARATUS FOR AVOIDING INTERRUPT OF AN INSEPARABLE OPERATION Apr 2, 1992 Abandoned
07/867721 SINGLE PHYSICAL MAIN STORAGE SHARED BY TWO OR MORE PROCESSORS EXECUTING RESPECTIVE OPERATING SYSTEMS Mar 26, 1992 Abandoned
Array ( [id] => 2928262 [patent_doc_number] => 05179710 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-01-12 [patent_title] => 'Interface for amplifying logic signal from a signal line having a predetermined logic state to supply power to peripheral device' [patent_app_type] => 1 [patent_app_number] => 7/851247 [patent_app_country] => US [patent_app_date] => 1992-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1505 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/179/05179710.pdf [firstpage_image] =>[orig_patent_app_number] => 851247 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/851247
Interface for amplifying logic signal from a signal line having a predetermined logic state to supply power to peripheral device Mar 12, 1992 Issued
Array ( [id] => 2930569 [patent_doc_number] => 05193193 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-03-09 [patent_title] => 'Bus control system for arbitrating requests with predetermined on/off time limitations' [patent_app_type] => 1 [patent_app_number] => 7/841908 [patent_app_country] => US [patent_app_date] => 1992-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 10254 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 439 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/193/05193193.pdf [firstpage_image] =>[orig_patent_app_number] => 841908 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/841908
Bus control system for arbitrating requests with predetermined on/off time limitations Feb 23, 1992 Issued
07/827945 SYSTEM AND METHOD FOR COMPILING TOWARDS A SUPER-PIPELINED ARCHITECTURE Feb 2, 1992 Abandoned
07/823465 MESSAGE COMMUNICATION PROCESSING APPARATUS AND METHOD FOR EFFICIENTLY HANDLING MESSAGES OF DIFFERENT LENGTHS Jan 21, 1992 Abandoned
Array ( [id] => 2924756 [patent_doc_number] => 05228130 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-07-13 [patent_title] => 'Multi-channel peripheral interface using selectively flaggable channel register sets for concurrent write in response to any selected channel register write instruction' [patent_app_type] => 1 [patent_app_number] => 7/809759 [patent_app_country] => US [patent_app_date] => 1991-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 8 [patent_no_of_words] => 12026 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/228/05228130.pdf [firstpage_image] =>[orig_patent_app_number] => 809759 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/809759
Multi-channel peripheral interface using selectively flaggable channel register sets for concurrent write in response to any selected channel register write instruction Dec 17, 1991 Issued
07/790961 SELF-PROGRAMMING MICROCONTROLLER Nov 11, 1991 Abandoned
Array ( [id] => 2946801 [patent_doc_number] => 05197141 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-03-23 [patent_title] => 'Software controlled method of issuing hardware control commands to memory controller from prefetch unit by combining request code and address specified in program instructions' [patent_app_type] => 1 [patent_app_number] => 7/785229 [patent_app_country] => US [patent_app_date] => 1991-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 6371 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/197/05197141.pdf [firstpage_image] =>[orig_patent_app_number] => 785229 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/785229
Software controlled method of issuing hardware control commands to memory controller from prefetch unit by combining request code and address specified in program instructions Oct 27, 1991 Issued
Array ( [id] => 3012333 [patent_doc_number] => 05359725 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-10-25 [patent_title] => 'Method of creating CD-ROM image of files of different format with proper directories to be read by respective operating systems' [patent_app_type] => 1 [patent_app_number] => 7/776661 [patent_app_country] => US [patent_app_date] => 1991-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3745 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 387 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/359/05359725.pdf [firstpage_image] =>[orig_patent_app_number] => 776661 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/776661
Method of creating CD-ROM image of files of different format with proper directories to be read by respective operating systems Oct 14, 1991 Issued
07/775864 POWER SEQUENCE SYSTEM Oct 14, 1991 Abandoned
Array ( [id] => 3532621 [patent_doc_number] => 05490251 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-06 [patent_title] => 'Method and apparatus for transmitting data over a signalling channel in a digital telecommunications network' [patent_app_type] => 1 [patent_app_number] => 7/742987 [patent_app_country] => US [patent_app_date] => 1991-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9354 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/490/05490251.pdf [firstpage_image] =>[orig_patent_app_number] => 742987 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/742987
Method and apparatus for transmitting data over a signalling channel in a digital telecommunications network Aug 8, 1991 Issued
Array ( [id] => 3133666 [patent_doc_number] => 05381531 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-10 [patent_title] => 'Data processor for selective simultaneous execution of a delay slot instruction and a second subsequent instruction the pair following a conditional branch instruction' [patent_app_type] => 1 [patent_app_number] => 7/727581 [patent_app_country] => US [patent_app_date] => 1991-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 15088 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 477 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/381/05381531.pdf [firstpage_image] =>[orig_patent_app_number] => 727581 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/727581
Data processor for selective simultaneous execution of a delay slot instruction and a second subsequent instruction the pair following a conditional branch instruction Jul 8, 1991 Issued
07/724180 SYSTEM AND METHOD FOR PROTECTING AND LICENSING SOFTWARE ON AN ELECTRONIC NETWORK Jun 30, 1991 Abandoned
07/722882 PROTECTION RING EXTENSION FOR COMPUTER WITH VIRTUAL MACHINE MODE Jun 27, 1991 Abandoned
07/722759 AUTOMATIC DISKETTE DETECTION METHOD AND APPARATUS Jun 26, 1991 Abandoned
07/717448 CO-PROCESSOR SUPPORTING ARCHITECTURE ADAPTED TO A PROCESSOR WHICH DOES NOT NATIVELY SUPPORT CO-PROCESSING Jun 18, 1991 Abandoned
07/716779 BUS CONTROL SYSTEM FOR ARBITRATING REQUESTS WITH PREDETERMINED ON/OFF TIME LIMITATIONS Jun 17, 1991 Abandoned
07/710861 DATA SEQUENCER FOR DISK DRIVE EMPLOYING DUAL FUNCTION OPCODES Jun 3, 1991 Abandoned
Array ( [id] => 3460663 [patent_doc_number] => 05386560 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-31 [patent_title] => 'Execution of page data transfer by PT processors and issuing of split start and test instructions by CPUs coordinated by queued tokens' [patent_app_type] => 1 [patent_app_number] => 7/704559 [patent_app_country] => US [patent_app_date] => 1991-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 10152 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 404 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/386/05386560.pdf [firstpage_image] =>[orig_patent_app_number] => 704559 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/704559
Execution of page data transfer by PT processors and issuing of split start and test instructions by CPUs coordinated by queued tokens May 22, 1991 Issued
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