Kenneth S. Kim

Array ( [id] => 3488322 [patent_doc_number] => 05432914 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-07-11 [patent_title] => 'Scanner interface system for transferring data to main and secondary processing units' [patent_app_type] => 1 [patent_app_number] => 7/703481 [patent_app_country] => US [patent_app_date] => 1991-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3559 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 305 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/432/05432914.pdf [firstpage_image] =>[orig_patent_app_number] => 703481 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3090061 [patent_doc_number] => 05297274 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-22 [patent_title] => 'Performance analysis of program in multithread OS by creating concurrently running thread generating breakpoint interrupts to active tracing monitor' [patent_app_type] => 1 [patent_app_number] => 7/685582 [patent_app_country] => US [patent_app_date] => 1991-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2234 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/297/05297274.pdf [firstpage_image] =>[orig_patent_app_number] => 685582 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3028638 [patent_doc_number] => 05341500 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-08-23 [patent_title] => 'Data processor with combined static and dynamic masking of operand for breakpoint operation' [patent_app_type] => 1 [patent_app_number] => 7/679478 [patent_app_country] => US [patent_app_date] => 1991-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5346 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/341/05341500.pdf [firstpage_image] =>[orig_patent_app_number] => 679478 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3110673 [patent_doc_number] => 05299319 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-29 [patent_title] => 'High performance interlock collapsing SCISM ALU apparatus' [patent_app_type] => 1 [patent_app_number] => 7/677079 [patent_app_country] => US [patent_app_date] => 1991-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 14895 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/299/05299319.pdf [firstpage_image] =>[orig_patent_app_number] => 677079 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3064657 [patent_doc_number] => 05307465 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-04-26 [patent_title] => 'System for updating network topology based on configuration obtained from subset configuration composition matrix and switching node connection matrix for the subset configuration' [patent_app_type] => 1 [patent_app_number] => 7/676971 [patent_app_country] => US [patent_app_date] => 1991-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 21 [patent_no_of_words] => 4963 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 377 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/307/05307465.pdf [firstpage_image] =>[orig_patent_app_number] => 676971 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3032611 [patent_doc_number] => 05303356 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-04-12 [patent_title] => 'System for issuing instructions for parallel execution subsequent to branch into a group of member instructions with compoundability in dictation tag' [patent_app_type] => 1 [patent_app_number] => 7/677685 [patent_app_country] => US [patent_app_date] => 1991-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 9484 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 390 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/303/05303356.pdf [firstpage_image] =>[orig_patent_app_number] => 677685 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3132992 [patent_doc_number] => 05450568 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-12 [patent_title] => 'Program generation method for solving differential equations using mesh variables and staggered variables' [patent_app_type] => 1 [patent_app_number] => 7/668257 [patent_app_country] => US [patent_app_date] => 1991-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 70 [patent_no_of_words] => 22856 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 467 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/450/05450568.pdf [firstpage_image] =>[orig_patent_app_number] => 668257 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3847461 [patent_doc_number] => 05740360 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-14 [patent_title] => 'Apparatus and method for resetting a microprocessor in the event of improper program execution' [patent_app_type] => 1 [patent_app_number] => 7/659683 [patent_app_country] => US [patent_app_date] => 1991-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5084 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/740/05740360.pdf [firstpage_image] =>[orig_patent_app_number] => 659683 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3108408 [patent_doc_number] => 05291612 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-01 [patent_title] => 'System for evaluating boolean expressions using total differential generating tree structured processing elements controlled by partial subfunction differentials' [patent_app_type] => 1 [patent_app_number] => 7/653183 [patent_app_country] => US [patent_app_date] => 1991-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 8357 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 321 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/291/05291612.pdf [firstpage_image] =>[orig_patent_app_number] => 653183 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3120587 [patent_doc_number] => 05418932 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-23 [patent_title] => 'Generation of width modulated pulses by relatively adjusting rising and falling edges upon comparison of counter with programmably stored values' [patent_app_type] => 1 [patent_app_number] => 7/649861 [patent_app_country] => US [patent_app_date] => 1991-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 47 [patent_no_of_words] => 17239 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 428 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/418/05418932.pdf [firstpage_image] =>[orig_patent_app_number] => 649861 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3107045 [patent_doc_number] => 05313606 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-05-17 [patent_title] => 'System for detecting boundary cross-over of instruction memory space using reduced number of address bits' [patent_app_type] => 1 [patent_app_number] => 7/642977 [patent_app_country] => US [patent_app_date] => 1991-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1901 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 460 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/313/05313606.pdf [firstpage_image] =>[orig_patent_app_number] => 642977 [rel_patent_id] =>[rel_patent_doc_number] =>)