Search

Kenneth S. Kim

Examiner (ID: 328)

Most Active Art Unit
2111
Art Unit(s)
2783, 2315, 2181, 2183, 2784, 2111, 1107, 2302, 2185
Total Applications
1565
Issued Applications
1268
Pending Applications
37
Abandoned Applications
262

Applications

Application numberTitle of the applicationFiling DateStatus
07/629478 EMULATOR CONFIGURATION SYSTEM Dec 17, 1990 Abandoned
Array ( [id] => 3118309 [patent_doc_number] => 05448736 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-05 [patent_title] => 'Method for generating a program comprised of such a portion of a series of operator-inputted commands as will produce an operator-selected one of a number of results' [patent_app_type] => 1 [patent_app_number] => 7/629377 [patent_app_country] => US [patent_app_date] => 1990-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 55 [patent_figures_cnt] => 79 [patent_no_of_words] => 17225 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 277 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/448/05448736.pdf [firstpage_image] =>[orig_patent_app_number] => 629377 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/629377
Method for generating a program comprised of such a portion of a series of operator-inputted commands as will produce an operator-selected one of a number of results Dec 17, 1990 Issued
07/627283 DESIGN EVALUATION APPARATUS Dec 12, 1990 Abandoned
Array ( [id] => 2896955 [patent_doc_number] => 05269007 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-12-07 [patent_title] => 'RISC system capable of simultaneously executing data interlocked shift and arithmetic/logic instructions in one clock cycle by bypassing register' [patent_app_type] => 1 [patent_app_number] => 7/609408 [patent_app_country] => US [patent_app_date] => 1990-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 8193 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 392 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/269/05269007.pdf [firstpage_image] =>[orig_patent_app_number] => 609408 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/609408
RISC system capable of simultaneously executing data interlocked shift and arithmetic/logic instructions in one clock cycle by bypassing register Nov 4, 1990 Issued
Array ( [id] => 2869293 [patent_doc_number] => 05083262 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-01-21 [patent_title] => 'Language bindings for graphics functions to enable one application program to be used in different processing environments' [patent_app_type] => 1 [patent_app_number] => 7/590327 [patent_app_country] => US [patent_app_date] => 1990-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 9915 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/083/05083262.pdf [firstpage_image] =>[orig_patent_app_number] => 590327 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/590327
Language bindings for graphics functions to enable one application program to be used in different processing environments Sep 26, 1990 Issued
07/579631 MICRODE LINKER /LOADER THAT GENERATES MICROCODE SEQUENCES FOR MRI SEQUENCER BY MODIFYING PREVIOUSLY GENERATED MICROCODE SEQUENCES Sep 9, 1990 Abandoned
07/499504 A PROGRAMMED SYSTEM HAVING SAFEGUARDED REMOTE LOADING OF A TERMINAL ACCESSED FROM A REMOTE COMPUTER Sep 9, 1990 Abandoned
07/576159 INFORMATION PROCESSING SYSTEM HAVING IMPROVED INTERFACE Aug 29, 1990 Abandoned
Array ( [id] => 2872714 [patent_doc_number] => 05150469 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-09-22 [patent_title] => 'System and method for processor pipeline control by selective signal deassertion' [patent_app_type] => 1 [patent_app_number] => 7/554131 [patent_app_country] => US [patent_app_date] => 1990-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 9229 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/150/05150469.pdf [firstpage_image] =>[orig_patent_app_number] => 554131 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/554131
System and method for processor pipeline control by selective signal deassertion Jul 12, 1990 Issued
Array ( [id] => 2745844 [patent_doc_number] => 05015623 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-05-14 [patent_title] => 'Planar Josephson device with a silver salt interlayer' [patent_app_type] => 1 [patent_app_number] => 7/549341 [patent_app_country] => US [patent_app_date] => 1990-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 1628 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/015/05015623.pdf [firstpage_image] =>[orig_patent_app_number] => 549341 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/549341
Planar Josephson device with a silver salt interlayer Jul 5, 1990 Issued
Array ( [id] => 3454329 [patent_doc_number] => 05430862 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-07-04 [patent_title] => 'Emulation of CISC instructions by RISC instructions using two pipelined stages for overlapped CISC decoding and RISC execution' [patent_app_type] => 1 [patent_app_number] => 7/546348 [patent_app_country] => US [patent_app_date] => 1990-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4140 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/430/05430862.pdf [firstpage_image] =>[orig_patent_app_number] => 546348 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/546348
Emulation of CISC instructions by RISC instructions using two pipelined stages for overlapped CISC decoding and RISC execution Jun 28, 1990 Issued
07/541477 MCROCONTROLLER PERIPHERAL EXPANSION BUS Jun 21, 1990 Abandoned
Array ( [id] => 2930728 [patent_doc_number] => 05193202 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-03-09 [patent_title] => 'Processor array with relocated operand physical address generator capable of data transfer to distant physical processor for each virtual processor while simulating dimensionally larger array processor' [patent_app_type] => 1 [patent_app_number] => 7/529947 [patent_app_country] => US [patent_app_date] => 1990-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 4596 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 607 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/193/05193202.pdf [firstpage_image] =>[orig_patent_app_number] => 529947 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/529947
Processor array with relocated operand physical address generator capable of data transfer to distant physical processor for each virtual processor while simulating dimensionally larger array processor May 28, 1990 Issued
07/528951 MULTI-DEVICE EMULATION May 24, 1990 Abandoned
Array ( [id] => 2924703 [patent_doc_number] => 05228127 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-07-13 [patent_title] => 'Clustered multiprocessor system with global controller connected to each cluster memory control unit for directing order from processor to different cluster processors' [patent_app_type] => 1 [patent_app_number] => 7/526687 [patent_app_country] => US [patent_app_date] => 1990-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 3376 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/228/05228127.pdf [firstpage_image] =>[orig_patent_app_number] => 526687 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/526687
Clustered multiprocessor system with global controller connected to each cluster memory control unit for directing order from processor to different cluster processors May 21, 1990 Issued
Array ( [id] => 2693734 [patent_doc_number] => 04996169 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-02-26 [patent_title] => 'Semiconductor laser assembly' [patent_app_type] => 1 [patent_app_number] => 7/525525 [patent_app_country] => US [patent_app_date] => 1990-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 3893 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/996/04996169.pdf [firstpage_image] =>[orig_patent_app_number] => 525525 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/525525
Semiconductor laser assembly May 17, 1990 Issued
Array ( [id] => 2899423 [patent_doc_number] => 05214763 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-05-25 [patent_title] => 'Digital computer system capable of processing two or more instructions in parallel and having a coche and instruction compounding mechanism' [patent_app_type] => 1 [patent_app_number] => 7/522291 [patent_app_country] => US [patent_app_date] => 1990-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 7658 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 477 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/214/05214763.pdf [firstpage_image] =>[orig_patent_app_number] => 522291 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/522291
Digital computer system capable of processing two or more instructions in parallel and having a coche and instruction compounding mechanism May 9, 1990 Issued
07/521827 MULTIPROCESSOR TYPE TIME VARYING IMAGE ENCODING SYSTEM AND IMAGE PROCESSOR May 9, 1990 Abandoned
07/519382 GENERAL PURPOSE COMPOUNDING TECHNIQUE FOR INSTRUCTION-LEVEL PARALLEL PROCESSORS May 3, 1990 Abandoned
07/519384 SYSTEM AND METHOD FOR OBTAINING PRALIEL EXISTING INSTRUCTIONSIN A PARTICULAR DATA PROCESSING CONFIGURATION BY COMPOUNDING INSTRUCTIONS May 3, 1990 Abandoned
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