| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 2934321
[patent_doc_number] => 05201056
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-04-06
[patent_title] => 'RISC microprocessor architecture with multi-bit tag extended instructions for selectively attaching tag from either instruction or input data to arithmetic operation output'
[patent_app_type] => 1
[patent_app_number] => 7/517865
[patent_app_country] => US
[patent_app_date] => 1990-05-02
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/201/05201056.pdf
[firstpage_image] =>[orig_patent_app_number] => 517865
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/517865 | RISC microprocessor architecture with multi-bit tag extended instructions for selectively attaching tag from either instruction or input data to arithmetic operation output | May 1, 1990 | Issued |
Array
(
[id] => 3502594
[patent_doc_number] => 05440705
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-08-08
[patent_title] => 'Address modulo adjust unit for a memory management unit for monolithic digital signal processor'
[patent_app_type] => 1
[patent_app_number] => 7/516984
[patent_app_country] => US
[patent_app_date] => 1990-04-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_no_of_words] => 9199
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/440/05440705.pdf
[firstpage_image] =>[orig_patent_app_number] => 516984
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/516984 | Address modulo adjust unit for a memory management unit for monolithic digital signal processor | Apr 29, 1990 | Issued |
Array
(
[id] => 3035235
[patent_doc_number] => 05327543
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-07-05
[patent_title] => 'System for selectively masking operand portions for processing thereof'
[patent_app_type] => 1
[patent_app_number] => 7/513034
[patent_app_country] => US
[patent_app_date] => 1990-04-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 11
[patent_no_of_words] => 7786
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[patent_words_short_claim] => 286
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/327/05327543.pdf
[firstpage_image] =>[orig_patent_app_number] => 513034
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/513034 | System for selectively masking operand portions for processing thereof | Apr 22, 1990 | Issued |
| 07/508691 | COMPUTER ABLE TO DETERMINE WHETHER OR NOT A DISPLAY IS CONNECTED TO IT IN ACCORDANCE WITH THE STATUS DATA STORED IN A REGISTER, AND METHOD OF DETECTING WHETHER OR NOT A DISPLAY IS CONNECTED TO A COMPUTER | Apr 12, 1990 | Abandoned |
Array
(
[id] => 2842693
[patent_doc_number] => 05175819
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-12-29
[patent_title] => 'Cascadable parallel to serial converter using tap shift registers and data shift registers while receiving input data from FIFO buffer'
[patent_app_type] => 1
[patent_app_number] => 7/500678
[patent_app_country] => US
[patent_app_date] => 1990-03-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 2
[patent_no_of_words] => 3601
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[pdf_file] => patents/05/175/05175819.pdf
[firstpage_image] =>[orig_patent_app_number] => 500678
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/500678 | Cascadable parallel to serial converter using tap shift registers and data shift registers while receiving input data from FIFO buffer | Mar 27, 1990 | Issued |
Array
(
[id] => 2991928
[patent_doc_number] => 05204967
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-04-20
[patent_title] => 'Sorting system using cascaded modules with levels of memory cells among which levels data are displaced along ordered path indicated by pointers'
[patent_app_type] => 1
[patent_app_number] => 7/492585
[patent_app_country] => US
[patent_app_date] => 1990-03-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 20
[patent_no_of_words] => 7123
[patent_no_of_claims] => 10
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[pdf_file] => patents/05/204/05204967.pdf
[firstpage_image] =>[orig_patent_app_number] => 492585
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/492585 | Sorting system using cascaded modules with levels of memory cells among which levels data are displaced along ordered path indicated by pointers | Mar 12, 1990 | Issued |
| 07/492680 | PARALLEL PROCESSOR COMPUTER SYSTEM WITH PROCESSOR SELECTION | Mar 12, 1990 | Abandoned |
| 07/486061 | EFFICIENT DATA PROCESSOR INSTRUMENTATION FOR SYSTEMATIC PROGRAM DEBUGGING AND DEVELOPMENT | Feb 26, 1990 | Abandoned |
| 07/471092 | PREFIX INSTRUCTION FOR MODIFICATION OF A SUBSEQUENT INSTRUCTION | Jan 25, 1990 | Abandoned |
| 07/469634 | A MACHINE FOR PROCESSING INTERRUPTED OUT-OF-ORDER INSTRUSTIONS | Jan 23, 1990 | Abandoned |
Array
(
[id] => 2946720
[patent_doc_number] => 05220656
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-06-15
[patent_title] => 'System for selecting control parameter for microinstruction execution unit using parameters and parameter selection signal decoded from instruction'
[patent_app_type] => 1
[patent_app_number] => 7/457413
[patent_app_country] => US
[patent_app_date] => 1989-12-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
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[patent_no_of_words] => 13609
[patent_no_of_claims] => 7
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[patent_words_short_claim] => 238
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/220/05220656.pdf
[firstpage_image] =>[orig_patent_app_number] => 457413
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/457413 | System for selecting control parameter for microinstruction execution unit using parameters and parameter selection signal decoded from instruction | Dec 25, 1989 | Issued |
| 07/450771 | A MERGE DEVICE USING FIFO BUFFERS | Dec 13, 1989 | Abandoned |
Array
(
[id] => 3102953
[patent_doc_number] => 05278974
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-01-11
[patent_title] => 'Method and apparatus for the dynamic adjustment of data transfer timing to equalize the bandwidths of two buses in a computer system having different bandwidths'
[patent_app_type] => 1
[patent_app_number] => 7/445983
[patent_app_country] => US
[patent_app_date] => 1989-12-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 5
[patent_no_of_words] => 12806
[patent_no_of_claims] => 26
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[patent_words_short_claim] => 22
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/278/05278974.pdf
[firstpage_image] =>[orig_patent_app_number] => 445983
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/445983 | Method and apparatus for the dynamic adjustment of data transfer timing to equalize the bandwidths of two buses in a computer system having different bandwidths | Dec 3, 1989 | Issued |
| 07/441656 | INTERFACE WITH AN ELECTRICAL SUPPLY AND COMPUTER INCLUDING SUCH AN INTERFACE | Nov 26, 1989 | Abandoned |
Array
(
[id] => 2882756
[patent_doc_number] => 05163136
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-11-10
[patent_title] => 'System for assembling playback data frames using indexed frame buffer group according to logical frame numbers in valid subcode or frame header'
[patent_app_type] => 1
[patent_app_number] => 7/436570
[patent_app_country] => US
[patent_app_date] => 1989-11-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[pdf_file] => patents/05/163/05163136.pdf
[firstpage_image] =>[orig_patent_app_number] => 436570
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/436570 | System for assembling playback data frames using indexed frame buffer group according to logical frame numbers in valid subcode or frame header | Nov 12, 1989 | Issued |
Array
(
[id] => 2928387
[patent_doc_number] => 05179717
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-01-12
[patent_title] => 'Sorting circuit using first and last buffer memories addressed by reference axis data and chain buffer memory addressed by datum number of the first and last buffer memories'
[patent_app_type] => 1
[patent_app_number] => 7/435277
[patent_app_country] => US
[patent_app_date] => 1989-11-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
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[pdf_file] => patents/05/179/05179717.pdf
[firstpage_image] =>[orig_patent_app_number] => 435277
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/435277 | Sorting circuit using first and last buffer memories addressed by reference axis data and chain buffer memory addressed by datum number of the first and last buffer memories | Nov 12, 1989 | Issued |
Array
(
[id] => 2670179
[patent_doc_number] => 04983541
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-01-08
[patent_title] => 'Semiconductor laser device fabrication'
[patent_app_type] => 1
[patent_app_number] => 7/437376
[patent_app_country] => US
[patent_app_date] => 1989-11-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[pdf_file] => patents/04/983/04983541.pdf
[firstpage_image] =>[orig_patent_app_number] => 437376
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/437376 | Semiconductor laser device fabrication | Nov 12, 1989 | Issued |
Array
(
[id] => 2872741
[patent_doc_number] => 05167028
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-11-24
[patent_title] => 'System for controlling task operation of slave processor by switching access to shared memory banks by master processor'
[patent_app_type] => 1
[patent_app_number] => 7/435053
[patent_app_country] => US
[patent_app_date] => 1989-11-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[pdf_file] => patents/05/167/05167028.pdf
[firstpage_image] =>[orig_patent_app_number] => 435053
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/435053 | System for controlling task operation of slave processor by switching access to shared memory banks by master processor | Nov 12, 1989 | Issued |
| 07/431924 | MERGING INTEGRATED CIRCUIT MASK DATABASES FORMED BY DIFFERENT DESIGN RULES THROUGH GLOBAL MASK DATABASE EDITS | Nov 5, 1989 | Abandoned |
Array
(
[id] => 2904756
[patent_doc_number] => 05210831
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-05-11
[patent_title] => 'Methods and apparatus for insulating a branch prediction mechanism from data dependent branch table updates that result from variable test operand locations'
[patent_app_type] => 1
[patent_app_number] => 7/429922
[patent_app_country] => US
[patent_app_date] => 1989-10-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/210/05210831.pdf
[firstpage_image] =>[orig_patent_app_number] => 429922
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/429922 | Methods and apparatus for insulating a branch prediction mechanism from data dependent branch table updates that result from variable test operand locations | Oct 29, 1989 | Issued |