Kenneth S. Kim

Array ( [id] => 2927918 [patent_doc_number] => 05179692 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-01-12 [patent_title] => 'Emulation device for driving a LCD with signals formatted for a CRT display' [patent_app_type] => 1 [patent_app_number] => 7/371941 [patent_app_country] => US [patent_app_date] => 1989-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4577 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/179/05179692.pdf [firstpage_image] =>[orig_patent_app_number] => 371941 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2946624 [patent_doc_number] => 05220652 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-06-15 [patent_title] => 'Computer application programs data input interface for handicapped persons responsive to multiple push buttons for selecting data stored in binary tree' [patent_app_type] => 1 [patent_app_number] => 7/370102 [patent_app_country] => US [patent_app_date] => 1989-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 26 [patent_no_of_words] => 6777 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/220/05220652.pdf [firstpage_image] =>[orig_patent_app_number] => 370102 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2879410 [patent_doc_number] => 05097532 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-03-17 [patent_title] => 'Circuit for enabling a cache using a flush input to circumvent a late noncachable address input' [patent_app_type] => 1 [patent_app_number] => 7/369454 [patent_app_country] => US [patent_app_date] => 1989-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2537 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/097/05097532.pdf [firstpage_image] =>[orig_patent_app_number] => 369454 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2742855 [patent_doc_number] => 05077657 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-12-31 [patent_title] => 'Emulator Assist unit which forms addresses of user instruction operands in response to emulator assist unit commands from host processor' [patent_app_type] => 1 [patent_app_number] => 7/367271 [patent_app_country] => US [patent_app_date] => 1989-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 4310 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/077/05077657.pdf [firstpage_image] =>[orig_patent_app_number] => 367271 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2803824 [patent_doc_number] => 05136697 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-08-04 [patent_title] => 'System for reducing delay for execution subsequent to correctly predicted branch instruction using fetch information stored with each block of instructions in cache' [patent_app_type] => 1 [patent_app_number] => 7/361870 [patent_app_country] => US [patent_app_date] => 1989-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4060 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 299 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/136/05136697.pdf [firstpage_image] =>[orig_patent_app_number] => 361870 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2843093 [patent_doc_number] => 05129035 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-07-07 [patent_title] => 'Method of generating a numerical calculation program which simulates a physical phenomenon represented by a partial differential equation using discretization based upon a control volume finite differential method' [patent_app_type] => 1 [patent_app_number] => 7/361283 [patent_app_country] => US [patent_app_date] => 1989-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 6749 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/129/05129035.pdf [firstpage_image] =>[orig_patent_app_number] => 361283 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2808842 [patent_doc_number] => 05144692 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-09-01 [patent_title] => 'System for controlling access by first system to portion of main memory dedicated exclusively to second system to facilitate input/output processing via first system' [patent_app_type] => 1 [patent_app_number] => 7/353113 [patent_app_country] => US [patent_app_date] => 1989-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 84 [patent_figures_cnt] => 134 [patent_no_of_words] => 77767 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/144/05144692.pdf [firstpage_image] =>[orig_patent_app_number] => 353113 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2799219 [patent_doc_number] => 05155824 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-10-13 [patent_title] => 'System for transferring selected data words between main memory and cache with multiple data words and multiple dirty bits for each address' [patent_app_type] => 1 [patent_app_number] => 7/351899 [patent_app_country] => US [patent_app_date] => 1989-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4619 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/155/05155824.pdf [firstpage_image] =>[orig_patent_app_number] => 351899 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2927345 [patent_doc_number] => 05179660 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-01-12 [patent_title] => 'System for reducing communications overhead in distributed database transactions by serializing in order related requests into single transmission message and receiving transmission response' [patent_app_type] => 1 [patent_app_number] => 7/352082 [patent_app_country] => US [patent_app_date] => 1989-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3294 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/179/05179660.pdf [firstpage_image] =>[orig_patent_app_number] => 352082 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2797740 [patent_doc_number] => 05142632 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-08-25 [patent_title] => 'Control unit for processing instruction using chained processing modules by providing downstream flow of operative commands and upstream validation information' [patent_app_type] => 1 [patent_app_number] => 7/349730 [patent_app_country] => US [patent_app_date] => 1989-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 5581 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 467 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/142/05142632.pdf [firstpage_image] =>[orig_patent_app_number] => 349730 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2980770 [patent_doc_number] => 05203005 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-04-13 [patent_title] => 'Cell structure for linear array wafer scale integration architecture with capability to open boundary I/O bus without neighbor acknowledgement' [patent_app_type] => 1 [patent_app_number] => 7/346203 [patent_app_country] => US [patent_app_date] => 1989-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 8912 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 324 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/203/05203005.pdf [firstpage_image] =>[orig_patent_app_number] => 346203 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2980788 [patent_doc_number] => 05203006 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-04-13 [patent_title] => 'System for selecting next instruction address between unit incremented address and address from table specified by operating condition signals' [patent_app_type] => 1 [patent_app_number] => 7/338823 [patent_app_country] => US [patent_app_date] => 1989-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 4462 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/203/05203006.pdf [firstpage_image] =>[orig_patent_app_number] => 338823 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2761971 [patent_doc_number] => 05072369 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-12-10 [patent_title] => 'Interface between buses attached with cached modules providing address space mapped cache coherent memory access with SNOOP hit memory updates' [patent_app_type] => 1 [patent_app_number] => 7/335173 [patent_app_country] => US [patent_app_date] => 1989-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 6856 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 539 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/072/05072369.pdf [firstpage_image] =>[orig_patent_app_number] => 335173 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2843828 [patent_doc_number] => 05129071 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-07-07 [patent_title] => 'Address translation apparatus in virtual machine system using a space identifier field for discriminating DATOFF (dynamic address translation off) virtual machines' [patent_app_type] => 1 [patent_app_number] => 7/331756 [patent_app_country] => US [patent_app_date] => 1989-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3894 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 352 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/129/05129071.pdf [firstpage_image] =>[orig_patent_app_number] => 331756 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2882912 [patent_doc_number] => 05163144 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-11-10 [patent_title] => 'System for releasing access status of an extended buffer memory from a deadlock state after a predetermined number of locked-out access requests' [patent_app_type] => 1 [patent_app_number] => 7/329274 [patent_app_country] => US [patent_app_date] => 1989-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4691 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 385 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/163/05163144.pdf [firstpage_image] =>[orig_patent_app_number] => 329274 [rel_patent_id] =>[rel_patent_doc_number] =>)