Search

Kenneth S. Kim

Examiner (ID: 328)

Most Active Art Unit
2111
Art Unit(s)
2783, 2315, 2181, 2183, 2784, 2111, 1107, 2302, 2185
Total Applications
1565
Issued Applications
1268
Pending Applications
37
Abandoned Applications
262

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10854141 [patent_doc_number] => 08880851 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-04 [patent_title] => 'Microprocessor that performs X86 ISA and arm ISA machine language program instructions by hardware translation into microinstructions executed by common execution pipeline' [patent_app_type] => utility [patent_app_number] => 13/224310 [patent_app_country] => US [patent_app_date] => 2011-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 19480 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13224310 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/224310
Microprocessor that performs X86 ISA and arm ISA machine language program instructions by hardware translation into microinstructions executed by common execution pipeline Aug 31, 2011 Issued
Array ( [id] => 9680469 [patent_doc_number] => 08819396 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-26 [patent_title] => 'Parallel processing using plural processing modules when processing time including parallel control overhead time is determined to be less than serial processing time' [patent_app_type] => utility [patent_app_number] => 13/223915 [patent_app_country] => US [patent_app_date] => 2011-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 44 [patent_no_of_words] => 27015 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13223915 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/223915
Parallel processing using plural processing modules when processing time including parallel control overhead time is determined to be less than serial processing time Aug 31, 2011 Issued
Array ( [id] => 8297320 [patent_doc_number] => 08225122 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-17 [patent_title] => 'Formatting power-on request by blade module in power-off state under auxiliary power in blade server system' [patent_app_type] => utility [patent_app_number] => 13/220432 [patent_app_country] => US [patent_app_date] => 2011-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2368 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13220432 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/220432
Formatting power-on request by blade module in power-off state under auxiliary power in blade server system Aug 28, 2011 Issued
Array ( [id] => 9592811 [patent_doc_number] => 08782376 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-15 [patent_title] => 'Vector instruction execution to load vector data in registers of plural vector units using offset addressing logic' [patent_app_type] => utility [patent_app_number] => 13/219321 [patent_app_country] => US [patent_app_date] => 2011-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 8887 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 330 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13219321 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/219321
Vector instruction execution to load vector data in registers of plural vector units using offset addressing logic Aug 25, 2011 Issued
Array ( [id] => 8260004 [patent_doc_number] => 08209519 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-26 [patent_title] => 'Suspending write back of valid data in pipeline register to register file and cancelling when overwritten by subsequent instruction' [patent_app_type] => utility [patent_app_number] => 13/187899 [patent_app_country] => US [patent_app_date] => 2011-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5022 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13187899 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/187899
Suspending write back of valid data in pipeline register to register file and cancelling when overwritten by subsequent instruction Jul 20, 2011 Issued
Array ( [id] => 6093978 [patent_doc_number] => 20110219214 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-08 [patent_title] => 'Microprocessor having novel operations' [patent_app_type] => utility [patent_app_number] => 13/108723 [patent_app_country] => US [patent_app_date] => 2011-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8255 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0219/20110219214.pdf [firstpage_image] =>[orig_patent_app_number] => 13108723 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/108723
Packing two packed signed data in registers with saturation May 15, 2011 Issued
Array ( [id] => 8285670 [patent_doc_number] => 08219787 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-10 [patent_title] => 'Early release of resources by proceeding to retire store operations from exception reporting stage but keeping in load/store queue' [patent_app_type] => utility [patent_app_number] => 13/103345 [patent_app_country] => US [patent_app_date] => 2011-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 6809 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13103345 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/103345
Early release of resources by proceeding to retire store operations from exception reporting stage but keeping in load/store queue May 8, 2011 Issued
Array ( [id] => 8120089 [patent_doc_number] => 08161269 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-17 [patent_title] => 'Determining length of instruction with address form field exclusive of evaluating instruction specific opcode in three byte escape opcode' [patent_app_type] => utility [patent_app_number] => 13/070908 [patent_app_country] => US [patent_app_date] => 2011-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 11301 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/161/08161269.pdf [firstpage_image] =>[orig_patent_app_number] => 13070908 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/070908
Determining length of instruction with address form field exclusive of evaluating instruction specific opcode in three byte escape opcode Mar 23, 2011 Issued
Array ( [id] => 8183092 [patent_doc_number] => 08180999 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-05-15 [patent_title] => 'Vertically tiered horizontally expandable micro grid system with bridge docking bay contoured by radial arms extending from central hub for coupling processor or power hubs' [patent_app_type] => utility [patent_app_number] => 13/048158 [patent_app_country] => US [patent_app_date] => 2011-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 106 [patent_figures_cnt] => 106 [patent_no_of_words] => 52360 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 385 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/180/08180999.pdf [firstpage_image] =>[orig_patent_app_number] => 13048158 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/048158
Vertically tiered horizontally expandable micro grid system with bridge docking bay contoured by radial arms extending from central hub for coupling processor or power hubs Mar 14, 2011 Issued
Array ( [id] => 6217616 [patent_doc_number] => 20110138151 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-09 [patent_title] => 'PROCESSING ELEMENTS, MIXED MODE PARALLEL PROCESSOR SYSTEM, PROCESSING METHOD BY PROCESSING ELEMENTS, MIXED MODE PARALLEL PROCESSOR METHOD, PROCESSING PROGRAM BY PROCESSING ELEMENTS AND MIXED MODE PARALLEL PROCESSING PROGRAM' [patent_app_type] => utility [patent_app_number] => 13/030952 [patent_app_country] => US [patent_app_date] => 2011-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8457 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20110138151.pdf [firstpage_image] =>[orig_patent_app_number] => 13030952 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/030952
Selecting broadcast SIMD instruction or cached MIMD instruction stored in local memory of one of plurality of processing elements for all elements in each unit Feb 17, 2011 Issued
Array ( [id] => 7770653 [patent_doc_number] => 20120036502 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-09 [patent_title] => 'CONSISTENCY CHECKING FOR TRANSLATED INTRUCTIONS' [patent_app_type] => utility [patent_app_number] => 13/021609 [patent_app_country] => US [patent_app_date] => 2011-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6010 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0036/20120036502.pdf [firstpage_image] =>[orig_patent_app_number] => 13021609 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/021609
Consistency checking of source instruction to execute previously translated instructions between copy made upon occurrence of write operation to memory and current version Feb 3, 2011 Issued
Array ( [id] => 9314970 [patent_doc_number] => 08656205 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-02-18 [patent_title] => 'Generating reference clocks in USB device by selecting control signal to oscillator form plural calibration units' [patent_app_type] => utility [patent_app_number] => 13/007663 [patent_app_country] => US [patent_app_date] => 2011-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4698 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13007663 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/007663
Generating reference clocks in USB device by selecting control signal to oscillator form plural calibration units Jan 15, 2011 Issued
Array ( [id] => 8303146 [patent_doc_number] => 20120185704 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-19 [patent_title] => 'SELF-ORGANIZED POWER AND ENERGY CONTROL AND MANAGEMENT SYSTEMS AND METHODS' [patent_app_type] => utility [patent_app_number] => 13/007314 [patent_app_country] => US [patent_app_date] => 2011-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4997 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13007314 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/007314
Data table structure for self-organized management of communication with functional modules coupled via backplane assembly based on received module description including control logic Jan 13, 2011 Issued
Array ( [id] => 9352394 [patent_doc_number] => 08671297 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-03-11 [patent_title] => 'Returning from power saving mode upon receiving a packet other than switch inhibiting packets classified as having interval shorter than switch waiting time to power saving mode' [patent_app_type] => utility [patent_app_number] => 13/006911 [patent_app_country] => US [patent_app_date] => 2011-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7952 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13006911 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/006911
Returning from power saving mode upon receiving a packet other than switch inhibiting packets classified as having interval shorter than switch waiting time to power saving mode Jan 13, 2011 Issued
Array ( [id] => 9089426 [patent_doc_number] => 08560873 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-10-15 [patent_title] => 'Determination of transitional characteristic attributes of components during scheduled wake-up power transition of computing device' [patent_app_type] => utility [patent_app_number] => 13/006070 [patent_app_country] => US [patent_app_date] => 2011-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 13817 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13006070 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/006070
Determination of transitional characteristic attributes of components during scheduled wake-up power transition of computing device Jan 12, 2011 Issued
Array ( [id] => 5990673 [patent_doc_number] => 20110099393 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-28 [patent_title] => 'MULTI-THREADING PROCESSORS, INTEGRATED CIRCUIT DEVICES, SYSTEMS, AND PROCESSES OF OPERATION AND MANUFACTURE' [patent_app_type] => utility [patent_app_number] => 12/986127 [patent_app_country] => US [patent_app_date] => 2011-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 51645 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0099/20110099393.pdf [firstpage_image] =>[orig_patent_app_number] => 12986127 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/986127
Managing power of thread pipelines according to clock frequency and voltage specified in thread registers Jan 5, 2011 Issued
Array ( [id] => 10890604 [patent_doc_number] => 08914617 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-16 [patent_title] => 'Tracking mechanism coupled to retirement in reorder buffer for indicating sharing logical registers of physical register in record indexed by logical register' [patent_app_type] => utility [patent_app_number] => 12/978513 [patent_app_country] => US [patent_app_date] => 2010-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5811 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12978513 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/978513
Tracking mechanism coupled to retirement in reorder buffer for indicating sharing logical registers of physical register in record indexed by logical register Dec 23, 2010 Issued
Array ( [id] => 9302141 [patent_doc_number] => 08650383 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-02-11 [patent_title] => 'Vector processing with predicate vector for setting element values based on key element position by executing remaining instruction' [patent_app_type] => utility [patent_app_number] => 12/977333 [patent_app_country] => US [patent_app_date] => 2010-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 25 [patent_no_of_words] => 36831 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12977333 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/977333
Vector processing with predicate vector for setting element values based on key element position by executing remaining instruction Dec 22, 2010 Issued
Array ( [id] => 8998089 [patent_doc_number] => 08521994 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-27 [patent_title] => 'Interleaving corresponding data elements from part of two source registers to destination register in processor operable to perform saturation' [patent_app_type] => utility [patent_app_number] => 12/975807 [patent_app_country] => US [patent_app_date] => 2010-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 8225 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12975807 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/975807
Interleaving corresponding data elements from part of two source registers to destination register in processor operable to perform saturation Dec 21, 2010 Issued
Array ( [id] => 6040611 [patent_doc_number] => 20110093660 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-21 [patent_title] => 'MULTI-CORE PROCESSING SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/972878 [patent_app_country] => US [patent_app_date] => 2010-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4932 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0093/20110093660.pdf [firstpage_image] =>[orig_patent_app_number] => 12972878 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/972878
Coherency groups of serially coupled processing cores propagating coherency information containing write packet to memory Dec 19, 2010 Issued
Menu