Search

Kenneth S. Kim

Examiner (ID: 7211)

Most Active Art Unit
2111
Art Unit(s)
2302, 2315, 2111, 2185, 2784, 2783, 1107, 2183, 2181
Total Applications
1565
Issued Applications
1267
Pending Applications
37
Abandoned Applications
262

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8998089 [patent_doc_number] => 08521994 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-27 [patent_title] => 'Interleaving corresponding data elements from part of two source registers to destination register in processor operable to perform saturation' [patent_app_type] => utility [patent_app_number] => 12/975807 [patent_app_country] => US [patent_app_date] => 2010-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 8225 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12975807 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/975807
Interleaving corresponding data elements from part of two source registers to destination register in processor operable to perform saturation Dec 21, 2010 Issued
Array ( [id] => 6040611 [patent_doc_number] => 20110093660 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-21 [patent_title] => 'MULTI-CORE PROCESSING SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/972878 [patent_app_country] => US [patent_app_date] => 2010-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4932 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0093/20110093660.pdf [firstpage_image] =>[orig_patent_app_number] => 12972878 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/972878
Coherency groups of serially coupled processing cores propagating coherency information containing write packet to memory Dec 19, 2010 Issued
Array ( [id] => 7493010 [patent_doc_number] => 20110238963 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-29 [patent_title] => 'RECONFIGURABLE ARRAY AND METHOD OF CONTROLLING THE RECONFIGURABLE ARRAY' [patent_app_type] => utility [patent_app_number] => 12/962741 [patent_app_country] => US [patent_app_date] => 2010-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3921 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0238/20110238963.pdf [firstpage_image] =>[orig_patent_app_number] => 12962741 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/962741
Analyzing data flow graph to detect data for copying from central register file to local register file used in different execution modes in reconfigurable processing array Dec 7, 2010 Issued
Array ( [id] => 9248424 [patent_doc_number] => 08612726 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-17 [patent_title] => 'Multi-cycle programmable processor with FSM implemented controller selectively altering functional units datapaths based on instruction type' [patent_app_type] => utility [patent_app_number] => 12/962441 [patent_app_country] => US [patent_app_date] => 2010-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3100 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 406 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12962441 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/962441
Multi-cycle programmable processor with FSM implemented controller selectively altering functional units datapaths based on instruction type Dec 6, 2010 Issued
Array ( [id] => 7671519 [patent_doc_number] => 20110320788 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-29 [patent_title] => 'METHOD AND APPARATUS FOR BRANCH REDUCTION IN A MULTITHREADED PACKET PROCESSOR' [patent_app_type] => utility [patent_app_number] => 12/951591 [patent_app_country] => US [patent_app_date] => 2010-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4382 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12951591 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/951591
Packet processor configured for processing features directed by branch instruction with logical operator and two feature selector fields Nov 21, 2010 Issued
Array ( [id] => 9499992 [patent_doc_number] => 08738832 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-05-27 [patent_title] => 'Microgrid apparatus with central area containing plural processors communicating via respective wireless connection point or bi-directional bus with module in docking bays defined by radial arms' [patent_app_type] => utility [patent_app_number] => 12/949059 [patent_app_country] => US [patent_app_date] => 2010-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 6256 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12949059 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/949059
Microgrid apparatus with central area containing plural processors communicating via respective wireless connection point or bi-directional bus with module in docking bays defined by radial arms Nov 17, 2010 Issued
Array ( [id] => 10841186 [patent_doc_number] => 08868885 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-21 [patent_title] => 'On-the-fly permutation of vector elements for executing successive elemental instructions' [patent_app_type] => utility [patent_app_number] => 12/949265 [patent_app_country] => US [patent_app_date] => 2010-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 7734 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 263 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12949265 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/949265
On-the-fly permutation of vector elements for executing successive elemental instructions Nov 17, 2010 Issued
Array ( [id] => 8201765 [patent_doc_number] => 20120124341 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-17 [patent_title] => 'Methods and Apparatus for Performing Multiple Operand Logical Operations in a Single Instruction' [patent_app_type] => utility [patent_app_number] => 12/947971 [patent_app_country] => US [patent_app_date] => 2010-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5386 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20120124341.pdf [firstpage_image] =>[orig_patent_app_number] => 12947971 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/947971
Methods and Apparatus for Performing Multiple Operand Logical Operations in a Single Instruction Nov 16, 2010 Abandoned
Array ( [id] => 6204048 [patent_doc_number] => 20110066834 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-17 [patent_title] => 'CONCURRENT EXCEPTION HANDLING' [patent_app_type] => utility [patent_app_number] => 12/948564 [patent_app_country] => US [patent_app_date] => 2010-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4112 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20110066834.pdf [firstpage_image] =>[orig_patent_app_number] => 12948564 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/948564
Concurrent handling of exceptions in received aggregate exception structure with supplied exception handlers and marking handled exceptions Nov 16, 2010 Issued
Array ( [id] => 9352365 [patent_doc_number] => 08671269 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-03-11 [patent_title] => 'Branch predictor accuracy by forwarding table updates to pending branch predictions' [patent_app_type] => utility [patent_app_number] => 12/947206 [patent_app_country] => US [patent_app_date] => 2010-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4441 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12947206 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/947206
Branch predictor accuracy by forwarding table updates to pending branch predictions Nov 15, 2010 Issued
Array ( [id] => 8201778 [patent_doc_number] => 20120124347 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-17 [patent_title] => 'BRANCH PREDICTION SCHEME UTILIZING PARTIAL-SIZED TARGETS' [patent_app_type] => utility [patent_app_number] => 12/945732 [patent_app_country] => US [patent_app_date] => 2010-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9762 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20120124347.pdf [firstpage_image] =>[orig_patent_app_number] => 12945732 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/945732
Generating predicted branch target address from two entries storing portions of target address based on static/dynamic indicator of branch instruction type Nov 11, 2010 Issued
Array ( [id] => 9348094 [patent_doc_number] => 08667257 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-03-04 [patent_title] => 'Detecting branch direction and target address pattern and supplying fetch address by replay unit instead of branch prediction unit' [patent_app_type] => utility [patent_app_number] => 12/943859 [patent_app_country] => US [patent_app_date] => 2010-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 10405 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12943859 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/943859
Detecting branch direction and target address pattern and supplying fetch address by replay unit instead of branch prediction unit Nov 9, 2010 Issued
Array ( [id] => 9102947 [patent_doc_number] => 08566841 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-22 [patent_title] => 'Processing communications events in parallel active messaging interface by awakening thread from wait state' [patent_app_type] => utility [patent_app_number] => 12/943105 [patent_app_country] => US [patent_app_date] => 2010-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 17812 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12943105 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/943105
Processing communications events in parallel active messaging interface by awakening thread from wait state Nov 9, 2010 Issued
Array ( [id] => 5960768 [patent_doc_number] => 20110185155 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-28 [patent_title] => 'MICROPROCESSOR THAT PERFORMS FAST REPEAT STRING LOADS' [patent_app_type] => utility [patent_app_number] => 12/942440 [patent_app_country] => US [patent_app_date] => 2010-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4445 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0185/20110185155.pdf [firstpage_image] =>[orig_patent_app_number] => 12942440 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/942440
Executing repeat load string instruction with guaranteed prefetch microcode to prefetch into cache for loading up to the last value in architectural register Nov 8, 2010 Issued
Array ( [id] => 8189207 [patent_doc_number] => 20120117360 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-10 [patent_title] => 'DEDICATED INSTRUCTIONS FOR VARIABLE LENGTH CODE INSERTION BY A DIGITAL SIGNAL PROCESSOR (DSP)' [patent_app_type] => utility [patent_app_number] => 12/942544 [patent_app_country] => US [patent_app_date] => 2010-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6239 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20120117360.pdf [firstpage_image] =>[orig_patent_app_number] => 12942544 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/942544
DEDICATED INSTRUCTIONS FOR VARIABLE LENGTH CODE INSERTION BY A DIGITAL SIGNAL PROCESSOR (DSP) Nov 8, 2010 Abandoned
Array ( [id] => 7510387 [patent_doc_number] => 08037284 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-11 [patent_title] => 'Stream processing in optically linked super node clusters of processors by mapping stream graph to nodes and links' [patent_app_type] => utility [patent_app_number] => 12/942492 [patent_app_country] => US [patent_app_date] => 2010-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4595 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 334 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/037/08037284.pdf [firstpage_image] =>[orig_patent_app_number] => 12942492 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/942492
Stream processing in optically linked super node clusters of processors by mapping stream graph to nodes and links Nov 8, 2010 Issued
Array ( [id] => 7653122 [patent_doc_number] => 20110302391 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-08 [patent_title] => 'DIGITAL SIGNAL PROCESSOR' [patent_app_type] => utility [patent_app_number] => 12/942310 [patent_app_country] => US [patent_app_date] => 2010-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2305 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0302/20110302391.pdf [firstpage_image] =>[orig_patent_app_number] => 12942310 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/942310
DSP performing instruction analyzed m-bit processing of data stored in memory with truncation / extension via data exchange unit Nov 8, 2010 Issued
Array ( [id] => 6073568 [patent_doc_number] => 20110047348 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-24 [patent_title] => 'PROCESSING ELEMENTS, MIXED MODE PARALLEL PROCESSOR SYSTEM, PROCESSING METHOD BY PROCESSING ELEMENTS, MIXED MODE PARALLEL PROCESSOR METHOD, PROCESSING PROGRAM BY PROCESSING ELEMENTS AND MIXED MODE PARALLEL PROCESSING PROGRAM' [patent_app_type] => utility [patent_app_number] => 12/917918 [patent_app_country] => US [patent_app_date] => 2010-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8430 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20110047348.pdf [firstpage_image] =>[orig_patent_app_number] => 12917918 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/917918
Supplying instruction stored in local memory configured as cache to peer processing elements in MIMD processing units Nov 1, 2010 Issued
Array ( [id] => 8319688 [patent_doc_number] => 08234483 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-31 [patent_title] => 'Memory units with packet processor for decapsulating read write access from and encapsulating response to external devices via serial packet switched protocol interface' [patent_app_type] => utility [patent_app_number] => 12/910867 [patent_app_country] => US [patent_app_date] => 2010-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6551 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 14 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12910867 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/910867
Memory units with packet processor for decapsulating read write access from and encapsulating response to external devices via serial packet switched protocol interface Oct 24, 2010 Issued
Array ( [id] => 4636928 [patent_doc_number] => 08015391 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-09-06 [patent_title] => 'Simultaneous multiple thread processor increasing number of instructions issued for thread detected to be processing loop' [patent_app_type] => utility [patent_app_number] => 12/900975 [patent_app_country] => US [patent_app_date] => 2010-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 28 [patent_no_of_words] => 8933 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/015/08015391.pdf [firstpage_image] =>[orig_patent_app_number] => 12900975 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/900975
Simultaneous multiple thread processor increasing number of instructions issued for thread detected to be processing loop Oct 7, 2010 Issued
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