Search

Kenneth T. Lam

Examiner (ID: 7525, Phone: (571)270-1862 , Office: P/2631 )

Most Active Art Unit
2631
Art Unit(s)
2631, 2611
Total Applications
1151
Issued Applications
929
Pending Applications
83
Abandoned Applications
150

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8647202 [patent_doc_number] => 20130032932 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-07 [patent_title] => 'BONDED WIRE SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/195042 [patent_app_country] => US [patent_app_date] => 2011-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2774 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13195042 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/195042
Bonded wire semiconductor device Jul 31, 2011 Issued
Array ( [id] => 8180205 [patent_doc_number] => 20120112330 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-10 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/195454 [patent_app_country] => US [patent_app_date] => 2011-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2231 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0112/20120112330.pdf [firstpage_image] =>[orig_patent_app_number] => 13195454 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/195454
SEMICONDUCTOR DEVICE Jul 31, 2011 Abandoned
Array ( [id] => 8995630 [patent_doc_number] => 08519517 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-27 [patent_title] => 'Semiconductor system with fine pitch lead fingers and method of manufacturing thereof' [patent_app_type] => utility [patent_app_number] => 13/194874 [patent_app_country] => US [patent_app_date] => 2011-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3314 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13194874 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/194874
Semiconductor system with fine pitch lead fingers and method of manufacturing thereof Jul 28, 2011 Issued
Array ( [id] => 7750627 [patent_doc_number] => 20120025395 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-02 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/193154 [patent_app_country] => US [patent_app_date] => 2011-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5070 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0025/20120025395.pdf [firstpage_image] =>[orig_patent_app_number] => 13193154 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/193154
Semiconductor device and method of manufacturing semiconductor device Jul 27, 2011 Issued
Array ( [id] => 8634812 [patent_doc_number] => 20130026615 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-31 [patent_title] => 'DOUBLE-SIDE EXPOSED SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD' [patent_app_type] => utility [patent_app_number] => 13/193474 [patent_app_country] => US [patent_app_date] => 2011-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2564 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13193474 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/193474
Double-side exposed semiconductor device and its manufacturing method Jul 27, 2011 Issued
Array ( [id] => 7750623 [patent_doc_number] => 20120025393 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-02 [patent_title] => 'Power Semiconductor Module, Method for Producing a Power Semiconductor Module and a Housing Element for a Power Semiconductor Module' [patent_app_type] => utility [patent_app_number] => 13/192323 [patent_app_country] => US [patent_app_date] => 2011-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5905 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0025/20120025393.pdf [firstpage_image] =>[orig_patent_app_number] => 13192323 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/192323
Power semiconductor module, method for producing a power semiconductor module and a housing element for a power semiconductor module Jul 26, 2011 Issued
Array ( [id] => 8249155 [patent_doc_number] => 20120153480 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-21 [patent_title] => 'Metallization Systems of Semiconductor Devices Comprising a Copper/Silicon Compound as a Barrier Material' [patent_app_type] => utility [patent_app_number] => 13/192164 [patent_app_country] => US [patent_app_date] => 2011-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6290 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20120153480.pdf [firstpage_image] =>[orig_patent_app_number] => 13192164 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/192164
Metallization systems of semiconductor devices comprising a copper/silicon compound as a barrier material Jul 26, 2011 Issued
Array ( [id] => 8572283 [patent_doc_number] => 08338933 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-25 [patent_title] => 'Three-dimensional package structure' [patent_app_type] => utility [patent_app_number] => 13/188774 [patent_app_country] => US [patent_app_date] => 2011-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 4425 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13188774 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/188774
Three-dimensional package structure Jul 21, 2011 Issued
Array ( [id] => 10898773 [patent_doc_number] => 08921995 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-12-30 [patent_title] => 'Integrated circuit package including a three-dimensional fan-out/fan-in signal routing' [patent_app_type] => utility [patent_app_number] => 13/183691 [patent_app_country] => US [patent_app_date] => 2011-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3318 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13183691 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/183691
Integrated circuit package including a three-dimensional fan-out/fan-in signal routing Jul 14, 2011 Issued
Array ( [id] => 7573616 [patent_doc_number] => 20110269272 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-03 [patent_title] => 'MICROELECTRONIC PACKAGES AND METHODS THEREFOR' [patent_app_type] => utility [patent_app_number] => 13/183122 [patent_app_country] => US [patent_app_date] => 2011-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 15045 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0269/20110269272.pdf [firstpage_image] =>[orig_patent_app_number] => 13183122 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/183122
Microelectronic packages and methods therefor Jul 13, 2011 Issued
Array ( [id] => 8544060 [patent_doc_number] => 08319354 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-27 [patent_title] => 'Semiconductor chip with post-passivation scheme formed over passivation layer' [patent_app_type] => utility [patent_app_number] => 13/181255 [patent_app_country] => US [patent_app_date] => 2011-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 30 [patent_no_of_words] => 8894 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 348 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13181255 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/181255
Semiconductor chip with post-passivation scheme formed over passivation layer Jul 11, 2011 Issued
Array ( [id] => 9692550 [patent_doc_number] => 08823152 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-09-02 [patent_title] => 'Semiconductor device with increased I/O leadframe' [patent_app_type] => utility [patent_app_number] => 13/181248 [patent_app_country] => US [patent_app_date] => 2011-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 37 [patent_no_of_words] => 17847 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13181248 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/181248
Semiconductor device with increased I/O leadframe Jul 11, 2011 Issued
Array ( [id] => 8955832 [patent_doc_number] => 08501604 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-06 [patent_title] => 'Method for forming a doped region in a semiconductor layer of a substrate and use of such method' [patent_app_type] => utility [patent_app_number] => 13/162507 [patent_app_country] => US [patent_app_date] => 2011-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 4408 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13162507 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/162507
Method for forming a doped region in a semiconductor layer of a substrate and use of such method Jun 15, 2011 Issued
Array ( [id] => 9020292 [patent_doc_number] => 08530277 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-10 [patent_title] => 'Integrated circuit packaging system with package on package support and method of manufacture thereof' [patent_app_type] => utility [patent_app_number] => 13/162526 [patent_app_country] => US [patent_app_date] => 2011-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4091 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13162526 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/162526
Integrated circuit packaging system with package on package support and method of manufacture thereof Jun 15, 2011 Issued
Array ( [id] => 8933207 [patent_doc_number] => 08492909 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-23 [patent_title] => 'Insulating member, metal base substrate, and semiconductor module, and manufacturing methods thereof' [patent_app_type] => utility [patent_app_number] => 13/162239 [patent_app_country] => US [patent_app_date] => 2011-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4226 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13162239 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/162239
Insulating member, metal base substrate, and semiconductor module, and manufacturing methods thereof Jun 15, 2011 Issued
Array ( [id] => 8519861 [patent_doc_number] => 20120319269 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-20 [patent_title] => 'Enhanced Bump Pitch Scaling' [patent_app_type] => utility [patent_app_number] => 13/162233 [patent_app_country] => US [patent_app_date] => 2011-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3742 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13162233 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/162233
Enhanced bump pitch scaling Jun 15, 2011 Issued
Array ( [id] => 8896590 [patent_doc_number] => 08476111 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-02 [patent_title] => 'Integrated circuit packaging system with intra substrate die and method of manufacture thereof' [patent_app_type] => utility [patent_app_number] => 13/162513 [patent_app_country] => US [patent_app_date] => 2011-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 14786 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13162513 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/162513
Integrated circuit packaging system with intra substrate die and method of manufacture thereof Jun 15, 2011 Issued
Array ( [id] => 8519862 [patent_doc_number] => 20120319270 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-20 [patent_title] => 'Wafer Level Chip Scale Package with Reduced Stress on Solder Balls' [patent_app_type] => utility [patent_app_number] => 13/162394 [patent_app_country] => US [patent_app_date] => 2011-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3218 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13162394 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/162394
Wafer level chip scale package with reduced stress on solder balls Jun 15, 2011 Issued
Array ( [id] => 9154220 [patent_doc_number] => 08587127 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-19 [patent_title] => 'Semiconductor structures and methods of forming the same' [patent_app_type] => utility [patent_app_number] => 13/161153 [patent_app_country] => US [patent_app_date] => 2011-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4651 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13161153 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/161153
Semiconductor structures and methods of forming the same Jun 14, 2011 Issued
Array ( [id] => 8519884 [patent_doc_number] => 20120319292 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-20 [patent_title] => 'STRUCTURE OF A WAFER LEVEL SUBSTRATE FOR CARRYING LIGHT EMITTING DEVICES' [patent_app_type] => utility [patent_app_number] => 13/161297 [patent_app_country] => US [patent_app_date] => 2011-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2458 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13161297 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/161297
STRUCTURE OF A WAFER LEVEL SUBSTRATE FOR CARRYING LIGHT EMITTING DEVICES Jun 14, 2011 Abandoned
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