Search

Kent Yip

Examiner (ID: 851, Phone: (571)270-5244 , Office: P/2676 )

Most Active Art Unit
2676
Art Unit(s)
2676, 2672, 2625, 2681
Total Applications
653
Issued Applications
467
Pending Applications
37
Abandoned Applications
155

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7407036 [patent_doc_number] => 20040175955 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-09 [patent_title] => 'Two stage etching of silicon nitride to form a nitride spacer' [patent_app_type] => new [patent_app_number] => 10/800190 [patent_app_country] => US [patent_app_date] => 2004-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5539 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0175/20040175955.pdf [firstpage_image] =>[orig_patent_app_number] => 10800190 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/800190
Two stage etching of silicon nitride to form a nitride spacer Mar 11, 2004 Issued
Array ( [id] => 7365400 [patent_doc_number] => 20040092130 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-13 [patent_title] => 'Method of manufacturing semiconductor device having metal alloy interconnection that has excellent EM lifetime' [patent_app_type] => new [patent_app_number] => 10/697335 [patent_app_country] => US [patent_app_date] => 2003-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6856 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0092/20040092130.pdf [firstpage_image] =>[orig_patent_app_number] => 10697335 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/697335
Method of manufacturing semiconductor device having metal alloy interconnection that has excellent EM lifetime Oct 30, 2003 Issued
Array ( [id] => 7465445 [patent_doc_number] => 20040166635 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-26 [patent_title] => 'Trench filling process for preventing formation of voids in trench' [patent_app_type] => new [patent_app_number] => 10/652635 [patent_app_country] => US [patent_app_date] => 2003-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1927 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0166/20040166635.pdf [firstpage_image] =>[orig_patent_app_number] => 10652635 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/652635
Trench filling process for preventing formation of voids in trench Aug 27, 2003 Issued
Array ( [id] => 7629831 [patent_doc_number] => 06818525 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-16 [patent_title] => 'Semiconductor device and method of providing regions of low substrate capacitance' [patent_app_type] => B1 [patent_app_number] => 10/632636 [patent_app_country] => US [patent_app_date] => 2003-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 14 [patent_no_of_words] => 2146 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 9 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/818/06818525.pdf [firstpage_image] =>[orig_patent_app_number] => 10632636 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/632636
Semiconductor device and method of providing regions of low substrate capacitance Aug 3, 2003 Issued
Array ( [id] => 1107552 [patent_doc_number] => 06808957 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-10-26 [patent_title] => 'Method for improving a high-speed edge-coupled photodetector' [patent_app_type] => B1 [patent_app_number] => 10/630935 [patent_app_country] => US [patent_app_date] => 2003-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 6043 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/808/06808957.pdf [firstpage_image] =>[orig_patent_app_number] => 10630935 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/630935
Method for improving a high-speed edge-coupled photodetector Jul 30, 2003 Issued
Array ( [id] => 7383837 [patent_doc_number] => 20040029397 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-12 [patent_title] => 'Method for fabricating semiconductor device' [patent_app_type] => new [patent_app_number] => 10/612941 [patent_app_country] => US [patent_app_date] => 2003-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1921 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0029/20040029397.pdf [firstpage_image] =>[orig_patent_app_number] => 10612941 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/612941
Method for fabricating semiconductor device Jul 6, 2003 Issued
Array ( [id] => 1107512 [patent_doc_number] => 06808942 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-10-26 [patent_title] => 'Method for controlling a critical dimension (CD) in an etch process' [patent_app_type] => B1 [patent_app_number] => 10/444345 [patent_app_country] => US [patent_app_date] => 2003-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3143 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/808/06808942.pdf [firstpage_image] =>[orig_patent_app_number] => 10444345 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/444345
Method for controlling a critical dimension (CD) in an etch process May 22, 2003 Issued
Array ( [id] => 6664188 [patent_doc_number] => 20030203514 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-30 [patent_title] => 'Method for determining a preceding wafer, method for determining a measuring wafer, and method for adjusting the number of wafers' [patent_app_type] => new [patent_app_number] => 10/431513 [patent_app_country] => US [patent_app_date] => 2003-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8402 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0203/20030203514.pdf [firstpage_image] =>[orig_patent_app_number] => 10431513 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/431513
Method for determining a preceding wafer, method for determining a measuring wafer, and method for adjusting the number of wafers May 7, 2003 Issued
Array ( [id] => 1056419 [patent_doc_number] => 06855642 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-02-15 [patent_title] => 'Method for fabricating semiconductor integrated circuit device' [patent_app_type] => utility [patent_app_number] => 10/424105 [patent_app_country] => US [patent_app_date] => 2003-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 34 [patent_no_of_words] => 18469 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/855/06855642.pdf [firstpage_image] =>[orig_patent_app_number] => 10424105 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/424105
Method for fabricating semiconductor integrated circuit device Apr 27, 2003 Issued
Array ( [id] => 1126746 [patent_doc_number] => 06790784 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-14 [patent_title] => 'Plasma treatment of low dielectric constant dielectric material to form structures useful in formation of metal interconnects and/or filled vias for intergrated circuit structure' [patent_app_type] => B2 [patent_app_number] => 10/422270 [patent_app_country] => US [patent_app_date] => 2003-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 6490 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 326 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/790/06790784.pdf [firstpage_image] =>[orig_patent_app_number] => 10422270 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/422270
Plasma treatment of low dielectric constant dielectric material to form structures useful in formation of metal interconnects and/or filled vias for intergrated circuit structure Apr 23, 2003 Issued
Array ( [id] => 6701742 [patent_doc_number] => 20030224622 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-04 [patent_title] => 'Insulation film on semiconductor substrate and method for forming same' [patent_app_type] => new [patent_app_number] => 10/402109 [patent_app_country] => US [patent_app_date] => 2003-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 7324 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0224/20030224622.pdf [firstpage_image] =>[orig_patent_app_number] => 10402109 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/402109
Insulation film on semiconductor substrate and method for forming same Mar 26, 2003 Issued
Array ( [id] => 1110852 [patent_doc_number] => 06806117 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-10-19 [patent_title] => 'Methods of testing/stressing a charge trapping device' [patent_app_type] => B2 [patent_app_number] => 10/322080 [patent_app_country] => US [patent_app_date] => 2002-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 34 [patent_no_of_words] => 22341 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/806/06806117.pdf [firstpage_image] =>[orig_patent_app_number] => 10322080 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/322080
Methods of testing/stressing a charge trapping device Dec 16, 2002 Issued
Array ( [id] => 7289730 [patent_doc_number] => 20040110337 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-10 [patent_title] => 'Adaptive negative differential resistance device' [patent_app_type] => new [patent_app_number] => 10/321090 [patent_app_country] => US [patent_app_date] => 2002-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 22669 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0110/20040110337.pdf [firstpage_image] =>[orig_patent_app_number] => 10321090 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/321090
Adaptive negative differential resistance device Dec 16, 2002 Issued
Array ( [id] => 6761510 [patent_doc_number] => 20030124872 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-03 [patent_title] => 'Combined gate cap or digit line and spacer deposition using HDP' [patent_app_type] => new [patent_app_number] => 10/319694 [patent_app_country] => US [patent_app_date] => 2002-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4127 [patent_no_of_claims] => 108 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20030124872.pdf [firstpage_image] =>[orig_patent_app_number] => 10319694 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/319694
Combined gate cap or digit line and spacer deposition using HDP Dec 15, 2002 Issued
Array ( [id] => 7289732 [patent_doc_number] => 20040110338 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-10 [patent_title] => 'Process for controlling performance characteristics of a negative differential resistance (NDR) device' [patent_app_type] => new [patent_app_number] => 10/314785 [patent_app_country] => US [patent_app_date] => 2002-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 15007 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0110/20040110338.pdf [firstpage_image] =>[orig_patent_app_number] => 10314785 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/314785
Process for controlling performance characteristics of a negative differential resistance (NDR) device Dec 8, 2002 Issued
Array ( [id] => 7289726 [patent_doc_number] => 20040110336 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-10 [patent_title] => 'Charge trapping device & method of forming the same' [patent_app_type] => new [patent_app_number] => 10/314510 [patent_app_country] => US [patent_app_date] => 2002-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 15000 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0110/20040110336.pdf [firstpage_image] =>[orig_patent_app_number] => 10314510 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/314510
Charge trapping device and method of forming the same Dec 8, 2002 Issued
Array ( [id] => 6657281 [patent_doc_number] => 20030077896 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-24 [patent_title] => 'Method of manufacturing semiconductor integrated circuit device having insulating film formed from liquid substance containning polymer of silicon, oxygen, and hydrogen' [patent_app_type] => new [patent_app_number] => 10/303935 [patent_app_country] => US [patent_app_date] => 2002-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 38 [patent_no_of_words] => 13998 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0077/20030077896.pdf [firstpage_image] =>[orig_patent_app_number] => 10303935 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/303935
Method of manufacturing semiconductor integrated circuit device having insulating film formed from liquid substance containing polymer of silicon, oxygen, and hydrogen Nov 25, 2002 Issued
Array ( [id] => 6649821 [patent_doc_number] => 20030104708 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-05 [patent_title] => 'CVD plasma assisted lower dielectric constant sicoh film' [patent_app_type] => new [patent_app_number] => 10/302240 [patent_app_country] => US [patent_app_date] => 2002-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7423 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0104/20030104708.pdf [firstpage_image] =>[orig_patent_app_number] => 10302240 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/302240
CVD plasma assisted lower dielectric constant SICOH film Nov 21, 2002 Issued
Array ( [id] => 6683472 [patent_doc_number] => 20030119336 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-26 [patent_title] => 'Insulation film on semiconductor substrate and method for forming same' [patent_app_type] => new [patent_app_number] => 10/288641 [patent_app_country] => US [patent_app_date] => 2002-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10027 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20030119336.pdf [firstpage_image] =>[orig_patent_app_number] => 10288641 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/288641
Insulation film on semiconductor substrate and method for forming same Nov 4, 2002 Issued
Array ( [id] => 1163632 [patent_doc_number] => 06759346 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-07-06 [patent_title] => 'Method of forming dielectric layers' [patent_app_type] => B1 [patent_app_number] => 10/270325 [patent_app_country] => US [patent_app_date] => 2002-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3126 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/759/06759346.pdf [firstpage_image] =>[orig_patent_app_number] => 10270325 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/270325
Method of forming dielectric layers Oct 14, 2002 Issued
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