Kent Yip

Array ( [id] => 6242511 [patent_doc_number] => 20020045342 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-18 [patent_title] => 'SEMICONDUCTOR STRUCTURE HAVING A DOPED CONDUCTIVE LAYER' [patent_app_type] => new [patent_app_number] => 09/455115 [patent_app_country] => US [patent_app_date] => 1999-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7299 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 22 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0045/20020045342.pdf [firstpage_image] =>[orig_patent_app_number] => 09455115 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4259518 [patent_doc_number] => 06258713 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Method for forming dual damascene structure' [patent_app_type] => 1 [patent_app_number] => 9/454005 [patent_app_country] => US [patent_app_date] => 1999-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 3518 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/258/06258713.pdf [firstpage_image] =>[orig_patent_app_number] => 454005 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4369413 [patent_doc_number] => 06287967 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Self-aligned silicide process' [patent_app_type] => 1 [patent_app_number] => 9/451585 [patent_app_country] => US [patent_app_date] => 1999-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1818 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/287/06287967.pdf [firstpage_image] =>[orig_patent_app_number] => 451585 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1435936 [patent_doc_number] => 06355579 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-12 [patent_title] => 'Method for forming gate oxide film in semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/442736 [patent_app_country] => US [patent_app_date] => 1999-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 23 [patent_no_of_words] => 3513 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/355/06355579.pdf [firstpage_image] =>[orig_patent_app_number] => 09442736 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4152443 [patent_doc_number] => 06124194 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-26 [patent_title] => 'Method of fabrication of anti-fuse integrated with dual damascene process' [patent_app_type] => 1 [patent_app_number] => 9/439365 [patent_app_country] => US [patent_app_date] => 1999-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1749 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/124/06124194.pdf [firstpage_image] =>[orig_patent_app_number] => 439365 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4382016 [patent_doc_number] => 06294482 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-25 [patent_title] => 'Method of forming an insulating layer pattern in a liquid crystal display' [patent_app_type] => 1 [patent_app_number] => 9/433957 [patent_app_country] => US [patent_app_date] => 1999-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 21 [patent_no_of_words] => 2825 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/294/06294482.pdf [firstpage_image] =>[orig_patent_app_number] => 433957 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1514563 [patent_doc_number] => 06420266 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-16 [patent_title] => 'Methods for creating elements of predetermined shape and apparatuses using these elements' [patent_app_type] => B1 [patent_app_number] => 09/433605 [patent_app_country] => US [patent_app_date] => 1999-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 38 [patent_no_of_words] => 7018 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/420/06420266.pdf [firstpage_image] =>[orig_patent_app_number] => 09433605 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4125740 [patent_doc_number] => 06127283 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'Method of electrophoretic deposition of ferroelectric films using a trifunctional additive and compositions for effecting same' [patent_app_type] => 1 [patent_app_number] => 9/432205 [patent_app_country] => US [patent_app_date] => 1999-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 10928 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/127/06127283.pdf [firstpage_image] =>[orig_patent_app_number] => 432205 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4286115 [patent_doc_number] => 06235354 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'Method of forming a level silicon oxide layer on two regions of different heights on a semiconductor wafer' [patent_app_type] => 1 [patent_app_number] => 9/431940 [patent_app_country] => US [patent_app_date] => 1999-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2037 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/235/06235354.pdf [firstpage_image] =>[orig_patent_app_number] => 431940 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1536237 [patent_doc_number] => 06337292 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-08 [patent_title] => 'Method of forming silicon oxide layer and method of manufacturing thin film transistor thereby' [patent_app_type] => B1 [patent_app_number] => 09/430037 [patent_app_country] => US [patent_app_date] => 1999-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 7677 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/337/06337292.pdf [firstpage_image] =>[orig_patent_app_number] => 09430037 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1459628 [patent_doc_number] => 06391795 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Low k dielectric composite layer for intergrated circuit structure which provides void-free low k dielectric material between metal lines while mitigating via poisoning' [patent_app_type] => B1 [patent_app_number] => 09/426056 [patent_app_country] => US [patent_app_date] => 1999-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5352 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/391/06391795.pdf [firstpage_image] =>[orig_patent_app_number] => 09426056 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4417490 [patent_doc_number] => 06194308 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-27 [patent_title] => 'Method of forming wire line' [patent_app_type] => 1 [patent_app_number] => 9/421165 [patent_app_country] => US [patent_app_date] => 1999-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 5428 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/194/06194308.pdf [firstpage_image] =>[orig_patent_app_number] => 421165 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4156673 [patent_doc_number] => 06156675 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-05 [patent_title] => 'Method for enhanced dielectric film uniformity' [patent_app_type] => 1 [patent_app_number] => 9/407575 [patent_app_country] => US [patent_app_date] => 1999-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3311 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/156/06156675.pdf [firstpage_image] =>[orig_patent_app_number] => 407575 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4294576 [patent_doc_number] => 06184129 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Low resistivity poly-silicon gate produced by selective metal growth' [patent_app_type] => 1 [patent_app_number] => 9/405265 [patent_app_country] => US [patent_app_date] => 1999-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 2904 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/184/06184129.pdf [firstpage_image] =>[orig_patent_app_number] => 405265 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4290596 [patent_doc_number] => 06235652 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'High rate silicon dioxide deposition at low pressures' [patent_app_type] => 1 [patent_app_number] => 9/396586 [patent_app_country] => US [patent_app_date] => 1999-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2863 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/235/06235652.pdf [firstpage_image] =>[orig_patent_app_number] => 396586 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4259430 [patent_doc_number] => 06204199 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-20 [patent_title] => 'Method for producing a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/393276 [patent_app_country] => US [patent_app_date] => 1999-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 17 [patent_no_of_words] => 9389 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/204/06204199.pdf [firstpage_image] =>[orig_patent_app_number] => 393276 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4152750 [patent_doc_number] => 06124216 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-26 [patent_title] => 'Method of making intermetal dielectric layers having a low dielectric constant' [patent_app_type] => 1 [patent_app_number] => 9/393185 [patent_app_country] => US [patent_app_date] => 1999-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2493 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/124/06124216.pdf [firstpage_image] =>[orig_patent_app_number] => 393185 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4407842 [patent_doc_number] => 06239041 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-29 [patent_title] => 'Method for fabricating semiconductor integrated circuit device' [patent_app_type] => 1 [patent_app_number] => 9/380646 [patent_app_country] => US [patent_app_date] => 1999-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 34 [patent_no_of_words] => 18371 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/239/06239041.pdf [firstpage_image] =>[orig_patent_app_number] => 380646 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4246809 [patent_doc_number] => 06221712 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'Method for fabricating gate oxide layer' [patent_app_type] => 1 [patent_app_number] => 9/385805 [patent_app_country] => US [patent_app_date] => 1999-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2942 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/221/06221712.pdf [firstpage_image] =>[orig_patent_app_number] => 385805 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4329441 [patent_doc_number] => 06313025 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-06 [patent_title] => 'Process for manufacturing an integrated circuit including a dual-damascene structure and an integrated circuit' [patent_app_type] => 1 [patent_app_number] => 9/385165 [patent_app_country] => US [patent_app_date] => 1999-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2065 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/313/06313025.pdf [firstpage_image] =>[orig_patent_app_number] => 385165 [rel_patent_id] =>[rel_patent_doc_number] =>)