Search

Kent Yip

Examiner (ID: 851, Phone: (571)270-5244 , Office: P/2676 )

Most Active Art Unit
2676
Art Unit(s)
2676, 2672, 2625, 2681
Total Applications
653
Issued Applications
467
Pending Applications
37
Abandoned Applications
155

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1490318 [patent_doc_number] => 06417099 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-09 [patent_title] => 'Method for controlling dopant diffusion in a plug-shaped doped polysilicon layer on a semiconductor wafer' [patent_app_type] => B1 [patent_app_number] => 09/148050 [patent_app_country] => US [patent_app_date] => 1998-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1696 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/417/06417099.pdf [firstpage_image] =>[orig_patent_app_number] => 09148050 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/148050
Method for controlling dopant diffusion in a plug-shaped doped polysilicon layer on a semiconductor wafer Sep 2, 1998 Issued
Array ( [id] => 4102236 [patent_doc_number] => 06100183 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'Method for fabricating a via' [patent_app_type] => 1 [patent_app_number] => 9/132384 [patent_app_country] => US [patent_app_date] => 1998-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 15 [patent_no_of_words] => 3572 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/100/06100183.pdf [firstpage_image] =>[orig_patent_app_number] => 132384 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/132384
Method for fabricating a via Aug 10, 1998 Issued
Array ( [id] => 4084189 [patent_doc_number] => 06162706 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-19 [patent_title] => 'Method of epitaxy on a silicon substrate comprising areas heavily doped with arsenic' [patent_app_type] => 1 [patent_app_number] => 9/124825 [patent_app_country] => US [patent_app_date] => 1998-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 2861 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/162/06162706.pdf [firstpage_image] =>[orig_patent_app_number] => 124825 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/124825
Method of epitaxy on a silicon substrate comprising areas heavily doped with arsenic Jul 28, 1998 Issued
Array ( [id] => 4294785 [patent_doc_number] => 06184143 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Semiconductor integrated circuit device and fabrication process thereof' [patent_app_type] => 1 [patent_app_number] => 9/123319 [patent_app_country] => US [patent_app_date] => 1998-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 59 [patent_figures_cnt] => 79 [patent_no_of_words] => 21961 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/184/06184143.pdf [firstpage_image] =>[orig_patent_app_number] => 123319 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/123319
Semiconductor integrated circuit device and fabrication process thereof Jul 27, 1998 Issued
Array ( [id] => 4404473 [patent_doc_number] => 06271069 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Method of making an article comprising an oxide layer on a GaAs-based semiconductor body' [patent_app_type] => 1 [patent_app_number] => 9/122558 [patent_app_country] => US [patent_app_date] => 1998-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 19 [patent_no_of_words] => 7740 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 318 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/271/06271069.pdf [firstpage_image] =>[orig_patent_app_number] => 122558 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/122558
Method of making an article comprising an oxide layer on a GaAs-based semiconductor body Jul 23, 1998 Issued
Array ( [id] => 3911636 [patent_doc_number] => 06001747 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-14 [patent_title] => 'Process to improve adhesion of cap layers in integrated circuits' [patent_app_type] => 1 [patent_app_number] => 9/120895 [patent_app_country] => US [patent_app_date] => 1998-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 2822 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/001/06001747.pdf [firstpage_image] =>[orig_patent_app_number] => 120895 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/120895
Process to improve adhesion of cap layers in integrated circuits Jul 21, 1998 Issued
Array ( [id] => 4214964 [patent_doc_number] => 06110818 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-29 [patent_title] => 'Semiconductor device with gate electrodes for sub-micron applications and fabrication thereof' [patent_app_type] => 1 [patent_app_number] => 9/115714 [patent_app_country] => US [patent_app_date] => 1998-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3332 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/110/06110818.pdf [firstpage_image] =>[orig_patent_app_number] => 115714 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/115714
Semiconductor device with gate electrodes for sub-micron applications and fabrication thereof Jul 14, 1998 Issued
Array ( [id] => 4156175 [patent_doc_number] => 06156640 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-05 [patent_title] => 'Damascene process with anti-reflection coating' [patent_app_type] => 1 [patent_app_number] => 9/115184 [patent_app_country] => US [patent_app_date] => 1998-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 3295 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/156/06156640.pdf [firstpage_image] =>[orig_patent_app_number] => 115184 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/115184
Damascene process with anti-reflection coating Jul 13, 1998 Issued
Array ( [id] => 4098152 [patent_doc_number] => 06048790 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-11 [patent_title] => 'Metalorganic decomposition deposition of thin conductive films on integrated circuits using reducing ambient' [patent_app_type] => 1 [patent_app_number] => 9/113436 [patent_app_country] => US [patent_app_date] => 1998-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3113 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/048/06048790.pdf [firstpage_image] =>[orig_patent_app_number] => 113436 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/113436
Metalorganic decomposition deposition of thin conductive films on integrated circuits using reducing ambient Jul 9, 1998 Issued
Array ( [id] => 1241187 [patent_doc_number] => 06683010 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-27 [patent_title] => 'Method for forming silicon-oxynitride layer on semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/104864 [patent_app_country] => US [patent_app_date] => 1998-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1625 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/683/06683010.pdf [firstpage_image] =>[orig_patent_app_number] => 09104864 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/104864
Method for forming silicon-oxynitride layer on semiconductor device Jun 24, 1998 Issued
Array ( [id] => 4355203 [patent_doc_number] => 06200901 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-13 [patent_title] => 'Polishing polymer surfaces on non-porous CMP pads' [patent_app_type] => 1 [patent_app_number] => 9/095299 [patent_app_country] => US [patent_app_date] => 1998-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 3595 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/200/06200901.pdf [firstpage_image] =>[orig_patent_app_number] => 095299 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/095299
Polishing polymer surfaces on non-porous CMP pads Jun 9, 1998 Issued
Array ( [id] => 4295008 [patent_doc_number] => 06184157 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Stress-loaded film and method for same' [patent_app_type] => 1 [patent_app_number] => 9/088456 [patent_app_country] => US [patent_app_date] => 1998-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 4002 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/184/06184157.pdf [firstpage_image] =>[orig_patent_app_number] => 088456 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/088456
Stress-loaded film and method for same May 31, 1998 Issued
Array ( [id] => 1490383 [patent_doc_number] => 06417115 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-09 [patent_title] => 'Treatment of dielectric materials' [patent_app_type] => B1 [patent_app_number] => 09/084238 [patent_app_country] => US [patent_app_date] => 1998-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5100 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/417/06417115.pdf [firstpage_image] =>[orig_patent_app_number] => 09084238 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/084238
Treatment of dielectric materials May 25, 1998 Issued
Array ( [id] => 4236294 [patent_doc_number] => 06143666 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-07 [patent_title] => 'Plasma surface treatment method for forming patterned TEOS based silicon oxide layer with reliable via and interconnection formed therethrough' [patent_app_type] => 1 [patent_app_number] => 9/050209 [patent_app_country] => US [patent_app_date] => 1998-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 9296 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/143/06143666.pdf [firstpage_image] =>[orig_patent_app_number] => 050209 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/050209
Plasma surface treatment method for forming patterned TEOS based silicon oxide layer with reliable via and interconnection formed therethrough Mar 29, 1998 Issued
Array ( [id] => 4130680 [patent_doc_number] => 06033998 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-07 [patent_title] => 'Method of forming variable thickness gate dielectrics' [patent_app_type] => 1 [patent_app_number] => 9/038684 [patent_app_country] => US [patent_app_date] => 1998-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 9 [patent_no_of_words] => 3954 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/033/06033998.pdf [firstpage_image] =>[orig_patent_app_number] => 038684 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/038684
Method of forming variable thickness gate dielectrics Mar 8, 1998 Issued
Array ( [id] => 4234171 [patent_doc_number] => 06074939 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-13 [patent_title] => 'Method for fabricating semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/030775 [patent_app_country] => US [patent_app_date] => 1998-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 4247 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/074/06074939.pdf [firstpage_image] =>[orig_patent_app_number] => 030775 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/030775
Method for fabricating semiconductor device Feb 25, 1998 Issued
Array ( [id] => 4189035 [patent_doc_number] => 06153525 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Methods for chemical mechanical polish of organic polymer dielectric films' [patent_app_type] => 1 [patent_app_number] => 9/023415 [patent_app_country] => US [patent_app_date] => 1998-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 4800 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/153/06153525.pdf [firstpage_image] =>[orig_patent_app_number] => 023415 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/023415
Methods for chemical mechanical polish of organic polymer dielectric films Feb 12, 1998 Issued
Array ( [id] => 4107121 [patent_doc_number] => 06022814 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-08 [patent_title] => 'Material of forming silicon oxide film, silicon oxide film, method of forming silicon oxide film and semiconductor element' [patent_app_type] => 1 [patent_app_number] => 9/022493 [patent_app_country] => US [patent_app_date] => 1998-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 21001 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/022/06022814.pdf [firstpage_image] =>[orig_patent_app_number] => 022493 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/022493
Material of forming silicon oxide film, silicon oxide film, method of forming silicon oxide film and semiconductor element Feb 11, 1998 Issued
Array ( [id] => 4354825 [patent_doc_number] => 06218318 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Semiconductor device having a porous insulation film' [patent_app_type] => 1 [patent_app_number] => 9/018855 [patent_app_country] => US [patent_app_date] => 1998-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 42 [patent_no_of_words] => 9064 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/218/06218318.pdf [firstpage_image] =>[orig_patent_app_number] => 018855 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/018855
Semiconductor device having a porous insulation film Feb 3, 1998 Issued
Array ( [id] => 4130693 [patent_doc_number] => 06033999 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-07 [patent_title] => 'Method of solving contact oblique problems of an ILD layer using a rapid thermal anneal' [patent_app_type] => 1 [patent_app_number] => 9/020584 [patent_app_country] => US [patent_app_date] => 1998-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 3159 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/033/06033999.pdf [firstpage_image] =>[orig_patent_app_number] => 020584 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/020584
Method of solving contact oblique problems of an ILD layer using a rapid thermal anneal Feb 1, 1998 Issued
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