Search

Kent Yip

Examiner (ID: 851, Phone: (571)270-5244 , Office: P/2676 )

Most Active Art Unit
2676
Art Unit(s)
2676, 2672, 2625, 2681
Total Applications
653
Issued Applications
467
Pending Applications
37
Abandoned Applications
155

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1119929 [patent_doc_number] => 06797652 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-09-28 [patent_title] => 'Copper damascene with low-k capping layer and improved electromigration reliability' [patent_app_type] => B1 [patent_app_number] => 10/097965 [patent_app_country] => US [patent_app_date] => 2002-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4474 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/797/06797652.pdf [firstpage_image] =>[orig_patent_app_number] => 10097965 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/097965
Copper damascene with low-k capping layer and improved electromigration reliability Mar 14, 2002 Issued
Array ( [id] => 1116994 [patent_doc_number] => 06800940 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-10-05 [patent_title] => 'Low k dielectric composite layer for integrated circuit structure which provides void-free low k dielectric material between metal lines while mitigating via poisoning' [patent_app_type] => B2 [patent_app_number] => 10/099641 [patent_app_country] => US [patent_app_date] => 2002-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5301 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/800/06800940.pdf [firstpage_image] =>[orig_patent_app_number] => 10099641 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/099641
Low k dielectric composite layer for integrated circuit structure which provides void-free low k dielectric material between metal lines while mitigating via poisoning Mar 14, 2002 Issued
Array ( [id] => 6716052 [patent_doc_number] => 20030027400 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-06 [patent_title] => 'SOI structure and method of producing same' [patent_app_type] => new [patent_app_number] => 10/096185 [patent_app_country] => US [patent_app_date] => 2002-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4399 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0027/20030027400.pdf [firstpage_image] =>[orig_patent_app_number] => 10096185 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/096185
SOI structure and method of producing same Mar 10, 2002 Issued
Array ( [id] => 1231494 [patent_doc_number] => 06693048 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-02-17 [patent_title] => 'High-pressure anneal process for integrated circuits' [patent_app_type] => B2 [patent_app_number] => 10/091936 [patent_app_country] => US [patent_app_date] => 2002-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1784 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/693/06693048.pdf [firstpage_image] =>[orig_patent_app_number] => 10091936 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/091936
High-pressure anneal process for integrated circuits Mar 4, 2002 Issued
Array ( [id] => 1126751 [patent_doc_number] => 06790786 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-14 [patent_title] => 'Etching processes for integrated circuit manufacturing including methods of forming capacitors' [patent_app_type] => B2 [patent_app_number] => 10/092875 [patent_app_country] => US [patent_app_date] => 2002-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 3003 [patent_no_of_claims] => 59 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/790/06790786.pdf [firstpage_image] =>[orig_patent_app_number] => 10092875 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/092875
Etching processes for integrated circuit manufacturing including methods of forming capacitors Mar 4, 2002 Issued
Array ( [id] => 5981993 [patent_doc_number] => 20020096733 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-25 [patent_title] => 'Pixel cell with high storage capacitance for a CMOS imager' [patent_app_type] => new [patent_app_number] => 10/086535 [patent_app_country] => US [patent_app_date] => 2002-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6016 [patent_no_of_claims] => 94 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0096/20020096733.pdf [firstpage_image] =>[orig_patent_app_number] => 10086535 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/086535
Pixel cell with high storage capacitance for a CMOS imager Mar 3, 2002 Issued
Array ( [id] => 6379222 [patent_doc_number] => 20020119663 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-29 [patent_title] => 'Method for forming a fine structure on a surface of a semiconductor material, semiconductor materials provided with such a fine structure, and devices made of such semiconductor materials' [patent_app_type] => new [patent_app_number] => 10/083615 [patent_app_country] => US [patent_app_date] => 2002-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4447 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20020119663.pdf [firstpage_image] =>[orig_patent_app_number] => 10083615 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/083615
Method for forming a fine structure on a surface of a semiconductor material, semiconductor materials provided with such a fine structure, and devices made of such semiconductor materials Feb 25, 2002 Abandoned
Array ( [id] => 1386708 [patent_doc_number] => 06548409 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-15 [patent_title] => 'Method of reducing micro-scratches during tungsten CMP' [patent_app_type] => B1 [patent_app_number] => 10/076395 [patent_app_country] => US [patent_app_date] => 2002-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 1343 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/548/06548409.pdf [firstpage_image] =>[orig_patent_app_number] => 10076395 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/076395
Method of reducing micro-scratches during tungsten CMP Feb 18, 2002 Issued
Array ( [id] => 6706368 [patent_doc_number] => 20030153102 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-14 [patent_title] => 'Method of controlling plasma etch process' [patent_app_type] => new [patent_app_number] => 10/076665 [patent_app_country] => US [patent_app_date] => 2002-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3217 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20030153102.pdf [firstpage_image] =>[orig_patent_app_number] => 10076665 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/076665
Method of controlling plasma etch process Feb 13, 2002 Issued
Array ( [id] => 5787479 [patent_doc_number] => 20020160606 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-31 [patent_title] => 'Method for material removal from an in-process microelectronic substrate' [patent_app_type] => new [patent_app_number] => 10/076115 [patent_app_country] => US [patent_app_date] => 2002-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6079 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0160/20020160606.pdf [firstpage_image] =>[orig_patent_app_number] => 10076115 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/076115
Method for material removal from an in-process microelectronic substrate Feb 13, 2002 Abandoned
Array ( [id] => 6706439 [patent_doc_number] => 20030153173 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-14 [patent_title] => 'Method of forming a novel top-metal fuse structure' [patent_app_type] => new [patent_app_number] => 10/075806 [patent_app_country] => US [patent_app_date] => 2002-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1947 [patent_no_of_claims] => 76 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20030153173.pdf [firstpage_image] =>[orig_patent_app_number] => 10075806 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/075806
Method of forming a novel top-metal fuse structure Feb 12, 2002 Issued
Array ( [id] => 1347618 [patent_doc_number] => 06579808 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-06-17 [patent_title] => 'Method of fabricating a semiconductor device' [patent_app_type] => B2 [patent_app_number] => 10/067955 [patent_app_country] => US [patent_app_date] => 2002-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 2024 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/579/06579808.pdf [firstpage_image] =>[orig_patent_app_number] => 10067955 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/067955
Method of fabricating a semiconductor device Feb 4, 2002 Issued
Array ( [id] => 1386442 [patent_doc_number] => 06548394 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-15 [patent_title] => 'Method of forming contact plugs' [patent_app_type] => B1 [patent_app_number] => 10/061646 [patent_app_country] => US [patent_app_date] => 2002-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 2549 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/548/06548394.pdf [firstpage_image] =>[orig_patent_app_number] => 10061646 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/061646
Method of forming contact plugs Jan 31, 2002 Issued
Array ( [id] => 1202748 [patent_doc_number] => 06720276 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-04-13 [patent_title] => 'Methods of forming spin on glass layers by curing remaining portions thereof' [patent_app_type] => B2 [patent_app_number] => 10/060486 [patent_app_country] => US [patent_app_date] => 2002-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2864 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/720/06720276.pdf [firstpage_image] =>[orig_patent_app_number] => 10060486 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/060486
Methods of forming spin on glass layers by curing remaining portions thereof Jan 29, 2002 Issued
Array ( [id] => 5986477 [patent_doc_number] => 20020098690 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-25 [patent_title] => 'Methods of forming semiconductor structures' [patent_app_type] => new [patent_app_number] => 10/062892 [patent_app_country] => US [patent_app_date] => 2002-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5152 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0098/20020098690.pdf [firstpage_image] =>[orig_patent_app_number] => 10062892 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/062892
Methods of forming semiconductor structures Jan 29, 2002 Issued
Array ( [id] => 1253385 [patent_doc_number] => 06670271 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-30 [patent_title] => 'Growing a dual damascene structure using a copper seed layer and a damascene resist structure' [patent_app_type] => B1 [patent_app_number] => 10/052146 [patent_app_country] => US [patent_app_date] => 2002-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 32 [patent_no_of_words] => 5711 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/670/06670271.pdf [firstpage_image] =>[orig_patent_app_number] => 10052146 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/052146
Growing a dual damascene structure using a copper seed layer and a damascene resist structure Jan 16, 2002 Issued
Array ( [id] => 1264582 [patent_doc_number] => 06660645 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-09 [patent_title] => 'Process for etching an organic dielectric using a silyated photoresist mask' [patent_app_type] => B1 [patent_app_number] => 10/051725 [patent_app_country] => US [patent_app_date] => 2002-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 2905 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/660/06660645.pdf [firstpage_image] =>[orig_patent_app_number] => 10051725 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/051725
Process for etching an organic dielectric using a silyated photoresist mask Jan 16, 2002 Issued
Array ( [id] => 1274097 [patent_doc_number] => 06649525 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-18 [patent_title] => 'Methods and systems for controlling resist residue defects at gate layer in a semiconductor device manufacturing process' [patent_app_type] => B1 [patent_app_number] => 10/050485 [patent_app_country] => US [patent_app_date] => 2002-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5762 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/649/06649525.pdf [firstpage_image] =>[orig_patent_app_number] => 10050485 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/050485
Methods and systems for controlling resist residue defects at gate layer in a semiconductor device manufacturing process Jan 15, 2002 Issued
Array ( [id] => 5968486 [patent_doc_number] => 20020090765 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-11 [patent_title] => 'Method of manufacturing a semiconductor device' [patent_app_type] => new [patent_app_number] => 10/044926 [patent_app_country] => US [patent_app_date] => 2002-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 12412 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0090/20020090765.pdf [firstpage_image] =>[orig_patent_app_number] => 10044926 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/044926
Method of manufacturing a semiconductor device Jan 14, 2002 Issued
Array ( [id] => 6659747 [patent_doc_number] => 20030134510 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-17 [patent_title] => 'Methods of forming metal layers in integrated circuit devices using selective deposition on edges of recesses and conductive contacts so formed' [patent_app_type] => new [patent_app_number] => 10/046805 [patent_app_country] => US [patent_app_date] => 2002-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6758 [patent_no_of_claims] => 62 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0134/20030134510.pdf [firstpage_image] =>[orig_patent_app_number] => 10046805 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/046805
Methods of forming metal layers in integrated circuit devices using selective deposition on edges of recesses and conductive contacts so formed Jan 13, 2002 Issued
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