Search

Kent Yip

Examiner (ID: 851, Phone: (571)270-5244 , Office: P/2676 )

Most Active Art Unit
2676
Art Unit(s)
2676, 2672, 2625, 2681
Total Applications
653
Issued Applications
467
Pending Applications
37
Abandoned Applications
155

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1474727 [patent_doc_number] => 06387828 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'High-pressure anneal process for integrated circuits' [patent_app_type] => B1 [patent_app_number] => 09/654029 [patent_app_country] => US [patent_app_date] => 2000-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1759 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/387/06387828.pdf [firstpage_image] =>[orig_patent_app_number] => 09654029 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/654029
High-pressure anneal process for integrated circuits Aug 30, 2000 Issued
Array ( [id] => 1459674 [patent_doc_number] => 06391805 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'High-pressure anneal process for integrated circuits' [patent_app_type] => B1 [patent_app_number] => 09/653120 [patent_app_country] => US [patent_app_date] => 2000-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1757 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/391/06391805.pdf [firstpage_image] =>[orig_patent_app_number] => 09653120 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/653120
High-pressure anneal process for integrated circuits Aug 30, 2000 Issued
Array ( [id] => 1169058 [patent_doc_number] => 06753270 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-22 [patent_title] => 'Process for depositing a porous, low dielectric constant silicon oxide film' [patent_app_type] => B1 [patent_app_number] => 09/632425 [patent_app_country] => US [patent_app_date] => 2000-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7894 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/753/06753270.pdf [firstpage_image] =>[orig_patent_app_number] => 09632425 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/632425
Process for depositing a porous, low dielectric constant silicon oxide film Aug 3, 2000 Issued
09/627296 METHOD AND DEVICE FOR MANUFACTURING SEMICONDUCTOR DEVICES INCLUDING INSULATION OXIDE LAYERS Jul 26, 2000 Abandoned
Array ( [id] => 1386993 [patent_doc_number] => 06548426 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-15 [patent_title] => 'Method for improving a quality of dielectric layer and semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/625355 [patent_app_country] => US [patent_app_date] => 2000-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 4564 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/548/06548426.pdf [firstpage_image] =>[orig_patent_app_number] => 09625355 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/625355
Method for improving a quality of dielectric layer and semiconductor device Jul 24, 2000 Issued
Array ( [id] => 4267757 [patent_doc_number] => 06306776 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'Catalytic breakdown of reactant gases in chemical vapor deposition' [patent_app_type] => 1 [patent_app_number] => 9/609345 [patent_app_country] => US [patent_app_date] => 2000-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2939 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/306/06306776.pdf [firstpage_image] =>[orig_patent_app_number] => 609345 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/609345
Catalytic breakdown of reactant gases in chemical vapor deposition Jul 4, 2000 Issued
Array ( [id] => 4304504 [patent_doc_number] => 06326319 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'Method for coating ultra-thin resist films' [patent_app_type] => 1 [patent_app_number] => 9/609746 [patent_app_country] => US [patent_app_date] => 2000-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1746 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/326/06326319.pdf [firstpage_image] =>[orig_patent_app_number] => 609746 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/609746
Method for coating ultra-thin resist films Jul 2, 2000 Issued
Array ( [id] => 1467089 [patent_doc_number] => 06458713 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-01 [patent_title] => 'Method for manufacturing semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/604726 [patent_app_country] => US [patent_app_date] => 2000-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 17 [patent_no_of_words] => 6526 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/458/06458713.pdf [firstpage_image] =>[orig_patent_app_number] => 09604726 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/604726
Method for manufacturing semiconductor device Jun 27, 2000 Issued
Array ( [id] => 1545471 [patent_doc_number] => 06444592 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-03 [patent_title] => 'Interfacial oxidation process for high-k gate dielectric process integration' [patent_app_type] => B1 [patent_app_number] => 09/597765 [patent_app_country] => US [patent_app_date] => 2000-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 3820 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/444/06444592.pdf [firstpage_image] =>[orig_patent_app_number] => 09597765 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/597765
Interfacial oxidation process for high-k gate dielectric process integration Jun 19, 2000 Issued
Array ( [id] => 7643946 [patent_doc_number] => 06429092 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-06 [patent_title] => 'Collar formation by selective oxide deposition' [patent_app_type] => B1 [patent_app_number] => 09/596606 [patent_app_country] => US [patent_app_date] => 2000-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3258 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 15 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/429/06429092.pdf [firstpage_image] =>[orig_patent_app_number] => 09596606 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/596606
Collar formation by selective oxide deposition Jun 18, 2000 Issued
Array ( [id] => 4267771 [patent_doc_number] => 06306777 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'Flash memory having a treatment layer disposed between an interpoly dielectric structure and method of forming' [patent_app_type] => 1 [patent_app_number] => 9/595166 [patent_app_country] => US [patent_app_date] => 2000-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3216 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/306/06306777.pdf [firstpage_image] =>[orig_patent_app_number] => 595166 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/595166
Flash memory having a treatment layer disposed between an interpoly dielectric structure and method of forming Jun 14, 2000 Issued
Array ( [id] => 1459517 [patent_doc_number] => 06391763 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Method for forming a plug or damascene trench on a semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/592146 [patent_app_country] => US [patent_app_date] => 2000-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1918 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/391/06391763.pdf [firstpage_image] =>[orig_patent_app_number] => 09592146 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/592146
Method for forming a plug or damascene trench on a semiconductor device Jun 11, 2000 Issued
Array ( [id] => 1466976 [patent_doc_number] => 06458655 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-01 [patent_title] => 'Method of manufacturing semiconductor device and flash memory' [patent_app_type] => B1 [patent_app_number] => 09/588475 [patent_app_country] => US [patent_app_date] => 2000-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 25 [patent_no_of_words] => 7333 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 322 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/458/06458655.pdf [firstpage_image] =>[orig_patent_app_number] => 09588475 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/588475
Method of manufacturing semiconductor device and flash memory Jun 6, 2000 Issued
Array ( [id] => 1441042 [patent_doc_number] => 06335261 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-01 [patent_title] => 'Directional CVD process with optimized etchback' [patent_app_type] => B1 [patent_app_number] => 09/584355 [patent_app_country] => US [patent_app_date] => 2000-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 3721 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/335/06335261.pdf [firstpage_image] =>[orig_patent_app_number] => 09584355 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/584355
Directional CVD process with optimized etchback May 30, 2000 Issued
Array ( [id] => 1390963 [patent_doc_number] => 06544901 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-08 [patent_title] => 'Plasma thin-film deposition method' [patent_app_type] => B1 [patent_app_number] => 09/578726 [patent_app_country] => US [patent_app_date] => 2000-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 28 [patent_no_of_words] => 7716 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/544/06544901.pdf [firstpage_image] =>[orig_patent_app_number] => 09578726 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/578726
Plasma thin-film deposition method May 25, 2000 Issued
Array ( [id] => 4327245 [patent_doc_number] => 06319812 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Method of manufacturing a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/577136 [patent_app_country] => US [patent_app_date] => 2000-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6066 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/319/06319812.pdf [firstpage_image] =>[orig_patent_app_number] => 577136 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/577136
Method of manufacturing a semiconductor device May 23, 2000 Issued
Array ( [id] => 1474709 [patent_doc_number] => 06387823 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'Method and apparatus for controlling deposition process using residual gas analysis' [patent_app_type] => B1 [patent_app_number] => 09/577756 [patent_app_country] => US [patent_app_date] => 2000-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3566 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/387/06387823.pdf [firstpage_image] =>[orig_patent_app_number] => 09577756 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/577756
Method and apparatus for controlling deposition process using residual gas analysis May 22, 2000 Issued
Array ( [id] => 1542753 [patent_doc_number] => 06372639 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Method for constructing interconnects for sub-micron semiconductor devices and the resulting semiconductor devices' [patent_app_type] => B1 [patent_app_number] => 09/576836 [patent_app_country] => US [patent_app_date] => 2000-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 22 [patent_no_of_words] => 10340 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/372/06372639.pdf [firstpage_image] =>[orig_patent_app_number] => 09576836 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/576836
Method for constructing interconnects for sub-micron semiconductor devices and the resulting semiconductor devices May 22, 2000 Issued
Array ( [id] => 1469941 [patent_doc_number] => 06407008 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-18 [patent_title] => 'Method of forming an oxide layer' [patent_app_type] => B1 [patent_app_number] => 09/564786 [patent_app_country] => US [patent_app_date] => 2000-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2522 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/407/06407008.pdf [firstpage_image] =>[orig_patent_app_number] => 09564786 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/564786
Method of forming an oxide layer May 4, 2000 Issued
Array ( [id] => 1459549 [patent_doc_number] => 06391774 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Fabrication process of semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/553315 [patent_app_country] => US [patent_app_date] => 2000-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 4963 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/391/06391774.pdf [firstpage_image] =>[orig_patent_app_number] => 09553315 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/553315
Fabrication process of semiconductor device Apr 19, 2000 Issued
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