Keri Jessica Nelson

Array ( [id] => 20640979 [patent_doc_number] => 20260099335 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-04-09 [patent_title] => Neural Processing Unit Leveraged Protocol to Provide Persistency [patent_app_type] => utility [patent_app_number] => 18/909125 [patent_app_country] => US [patent_app_date] => 2024-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5816 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18909125 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20680612 [patent_doc_number] => 20260119433 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-04-30 [patent_title] => SERVER SYSTEM, JOB EXECUTION METHOD AND APPARATUS, DEVICE, AND MEDIUM [patent_app_type] => utility [patent_app_number] => 19/470341 [patent_app_country] => US [patent_app_date] => 2024-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3779 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19470341 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20351545 [patent_doc_number] => 20250348397 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-13 [patent_title] => POWER MANAGEMENT METHOD AND POWER MANAGEMENT DEVICE [patent_app_type] => utility [patent_app_number] => 18/819526 [patent_app_country] => US [patent_app_date] => 2024-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18819526 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20543427 [patent_doc_number] => 20260050318 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-02-19 [patent_title] => ENERGY EFFICIENCY USING A POWER SAVING CLOCK BUFFER FOR CLOCK GRID-BASED SCANNING [patent_app_type] => utility [patent_app_number] => 18/805984 [patent_app_country] => US [patent_app_date] => 2024-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2521 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18805984 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20757951 [patent_doc_number] => 12650720 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-09 [patent_title] => Sleep/wake-up method, system, and apparatus [patent_app_type] => utility [patent_app_number] => 18/799394 [patent_app_country] => US [patent_app_date] => 2024-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 23 [patent_no_of_words] => 10230 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18799394 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19748016 [patent_doc_number] => 20250036581 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-30 [patent_title] => FLASH MEMORY DEVICE HAVING A CALIBRATION MODE [patent_app_type] => utility [patent_app_number] => 18/770876 [patent_app_country] => US [patent_app_date] => 2024-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8072 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18770876 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19772104 [patent_doc_number] => 20250053530 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-13 [patent_title] => HIGHLY SCALABLE ACCELERATOR [patent_app_type] => utility [patent_app_number] => 18/749130 [patent_app_country] => US [patent_app_date] => 2024-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9150 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18749130 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20408596 [patent_doc_number] => 20250377705 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-11 [patent_title] => Process And Temperature-aware Processor low-power mode Selection [patent_app_type] => utility [patent_app_number] => 18/734126 [patent_app_country] => US [patent_app_date] => 2024-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13305 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18734126 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19617386 [patent_doc_number] => 20240403066 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => SYSTEM AND METHOD FOR RESTRICTING ACCESS TO A RESOURCE [patent_app_type] => utility [patent_app_number] => 18/676689 [patent_app_country] => US [patent_app_date] => 2024-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6659 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18676689 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20447081 [patent_doc_number] => 20260003803 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-01 [patent_title] => DATA ACCESS METHOD, SWITCH AND STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 19/115274 [patent_app_country] => US [patent_app_date] => 2024-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3441 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19115274 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20249848 [patent_doc_number] => 20250298717 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-25 [patent_title] => DEEP LEARNING DATA COMPRESSION USING MULTIPLE HARDWARE ACCELERATOR ARCHITECTURES [patent_app_type] => utility [patent_app_number] => 18/611228 [patent_app_country] => US [patent_app_date] => 2024-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1095 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18611228 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20234444 [patent_doc_number] => 20250291763 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-18 [patent_title] => CAPABILITIES AND INTERFACES IN A FIRMWARE FRAMEWORK [patent_app_type] => utility [patent_app_number] => 18/602367 [patent_app_country] => US [patent_app_date] => 2024-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9419 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18602367 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20234285 [patent_doc_number] => 20250291604 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-18 [patent_title] => ARCHITECTURE FOR MICROCONTROLLER-BASED PLUG AND PLAY EDGE AI USB CAMERA [patent_app_type] => utility [patent_app_number] => 18/602119 [patent_app_country] => US [patent_app_date] => 2024-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1741 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18602119 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20181228 [patent_doc_number] => 20250265186 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-21 [patent_title] => ALLOCATING DATA STORAGE DEVICE RESOURCES BASED ON DETERMINED CAPABILITIES OF A HOST DEVICE [patent_app_type] => utility [patent_app_number] => 18/583061 [patent_app_country] => US [patent_app_date] => 2024-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4599 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18583061 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20180973 [patent_doc_number] => 20250264931 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-21 [patent_title] => Analog Voltage Shifter on Power Management Unit (PMU) Supply [patent_app_type] => utility [patent_app_number] => 18/582630 [patent_app_country] => US [patent_app_date] => 2024-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2466 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18582630 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19942444 [patent_doc_number] => 12314575 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-27 [patent_title] => Memory system and operations of the same [patent_app_type] => utility [patent_app_number] => 18/434429 [patent_app_country] => US [patent_app_date] => 2024-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 13447 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18434429 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20481589 [patent_doc_number] => 12530064 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-20 [patent_title] => Power aware thermal mitigation framework [patent_app_type] => utility [patent_app_number] => 18/428959 [patent_app_country] => US [patent_app_date] => 2024-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3094 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18428959 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20137775 [patent_doc_number] => 20250244819 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-31 [patent_title] => ENHANCED CURRENT LIMITING TECHNIQUES [patent_app_type] => utility [patent_app_number] => 18/427959 [patent_app_country] => US [patent_app_date] => 2024-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1130 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18427959 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19251168 [patent_doc_number] => 20240202158 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => SYSTEM COMMUNICATION TECHNIQUE OVER PCIe (PERIPHERAL COMPONENT INTERCONNECT EXPRESS) LINK [patent_app_type] => utility [patent_app_number] => 18/427692 [patent_app_country] => US [patent_app_date] => 2024-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14743 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18427692 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20215137 [patent_doc_number] => 12411790 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-09 [patent_title] => On-chip integrated circuit, data processing device, and data processing method [patent_app_type] => utility [patent_app_number] => 18/414920 [patent_app_country] => US [patent_app_date] => 2024-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 0 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18414920 [rel_patent_id] =>[rel_patent_doc_number] =>)