Kesha Frisby

Array ( [id] => 17173805 [patent_doc_number] => 20210327476 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-21 [patent_title] => MEMORY DEVICE, MEMORY SYSTEM, AND OPERATION METHOD OF MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/355765 [patent_app_country] => US [patent_app_date] => 2021-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8310 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17355765 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17708228 [patent_doc_number] => 20220208236 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => SEMICONDUCTOR DEVICE FOR SETTING OPTIONS OF I/O INTERFACE CIRCUITS [patent_app_type] => utility [patent_app_number] => 17/346708 [patent_app_country] => US [patent_app_date] => 2021-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8451 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17346708 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17660488 [patent_doc_number] => 20220180953 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-09 [patent_title] => STORAGE DEVICE AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/344264 [patent_app_country] => US [patent_app_date] => 2021-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13646 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17344264 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17115285 [patent_doc_number] => 20210295882 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-23 [patent_title] => MEMORY SYSTEM CAPABLE OF IMPROVING STABILITY OF A DATA READ OPERATION OF INTERFACE CIRCUIT, AND METHOD OF OPERATING THE MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/343027 [patent_app_country] => US [patent_app_date] => 2021-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11424 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17343027 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17115286 [patent_doc_number] => 20210295883 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-23 [patent_title] => MEMORY SYSTEM CAPABLE OF IMPROVING STABILITY OF A DATA READ OPERATION OF INTERFACE CIRCUIT, AND METHOD OF OPERATING THE MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/343046 [patent_app_country] => US [patent_app_date] => 2021-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11425 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17343046 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18061474 [patent_doc_number] => 20220392560 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-08 [patent_title] => ADJUSTABLE PROGRAMMING PULSES FOR A MULTI-LEVEL CELL [patent_app_type] => utility [patent_app_number] => 17/337195 [patent_app_country] => US [patent_app_date] => 2021-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14982 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17337195 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17431430 [patent_doc_number] => 20220059139 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-24 [patent_title] => METHOD OF GENERATING A MULTI-LEVEL SIGNAL USING A SELECTIVE LEVEL CHANGE, A METHOD OF TRANSMITTING DATA USING THE SAME, AND A TRANSMITTER AND MEMORY SYSTEM PERFORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/323009 [patent_app_country] => US [patent_app_date] => 2021-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15197 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17323009 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18304262 [patent_doc_number] => 11626175 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-11 [patent_title] => Memory system and operating method for determining target memory block for refreshing operation [patent_app_type] => utility [patent_app_number] => 17/321649 [patent_app_country] => US [patent_app_date] => 2021-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 11009 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17321649 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18008232 [patent_doc_number] => 20220366999 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-17 [patent_title] => Adaptive Read Disturb Algorithm For Nand Storage Accounting For Layer-Based Effect [patent_app_type] => utility [patent_app_number] => 17/322543 [patent_app_country] => US [patent_app_date] => 2021-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5734 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17322543 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18593137 [patent_doc_number] => 11742046 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-29 [patent_title] => Semiconductor memory device and operation method of swizzling data [patent_app_type] => utility [patent_app_number] => 17/318234 [patent_app_country] => US [patent_app_date] => 2021-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 13892 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17318234 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17795335 [patent_doc_number] => 20220254427 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-11 [patent_title] => APPARATUS CONFIGURED TO PERFORM A TEST OPERATION [patent_app_type] => utility [patent_app_number] => 17/306603 [patent_app_country] => US [patent_app_date] => 2021-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8971 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17306603 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17956148 [patent_doc_number] => 11482261 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-25 [patent_title] => Memory device and method of operating with different input/output modes [patent_app_type] => utility [patent_app_number] => 17/242988 [patent_app_country] => US [patent_app_date] => 2021-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 16042 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17242988 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18593099 [patent_doc_number] => 11742008 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-29 [patent_title] => Memory device with a clocking mechanism [patent_app_type] => utility [patent_app_number] => 17/240921 [patent_app_country] => US [patent_app_date] => 2021-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 7017 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17240921 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18357671 [patent_doc_number] => 11646077 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-09 [patent_title] => Memory sub-system grading and allocation [patent_app_type] => utility [patent_app_number] => 17/240014 [patent_app_country] => US [patent_app_date] => 2021-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 10217 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17240014 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17551345 [patent_doc_number] => 20220122687 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-21 [patent_title] => MEMORY DEVICE AND OPERATING METHOD OF THE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/238957 [patent_app_country] => US [patent_app_date] => 2021-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8102 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17238957 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18031793 [patent_doc_number] => 11514988 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-29 [patent_title] => Controller and method of operating under sudden power interruption [patent_app_type] => utility [patent_app_number] => 17/238784 [patent_app_country] => US [patent_app_date] => 2021-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 20 [patent_no_of_words] => 14257 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17238784 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17010643 [patent_doc_number] => 20210241804 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-05 [patent_title] => APPARATUS AND METHOD FOR IMPROVING INPUT/OUTPUT THROUGHPUT OF MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/234624 [patent_app_country] => US [patent_app_date] => 2021-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19897 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17234624 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18623585 [patent_doc_number] => 11756638 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-12 [patent_title] => End of life performance throttling to prevent data loss [patent_app_type] => utility [patent_app_number] => 17/232804 [patent_app_country] => US [patent_app_date] => 2021-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10733 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17232804 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18304316 [patent_doc_number] => 11626229 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-11 [patent_title] => Switching of perpendicularly magnetized nanomagnets with spin-orbit torques in the absence of external magnetic fields [patent_app_type] => utility [patent_app_number] => 17/231277 [patent_app_country] => US [patent_app_date] => 2021-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2716 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17231277 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19487099 [patent_doc_number] => 12106823 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-01 [patent_title] => Semiconductor device using transistors having low off-state current [patent_app_type] => utility [patent_app_number] => 17/914845 [patent_app_country] => US [patent_app_date] => 2021-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 60 [patent_no_of_words] => 33495 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17914845 [rel_patent_id] =>[rel_patent_doc_number] =>)