Search

Kesha Frisby

Examiner (ID: 18159, Phone: (571)272-8774 , Office: P/3715 )

Most Active Art Unit
3715
Art Unit(s)
3714, 3715
Total Applications
954
Issued Applications
470
Pending Applications
70
Abandoned Applications
432

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17825572 [patent_doc_number] => 11430524 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-30 [patent_title] => Method for designing an initialization function for programming a memory element [patent_app_type] => utility [patent_app_number] => 17/085071 [patent_app_country] => US [patent_app_date] => 2020-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 11259 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17085071 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/085071
Method for designing an initialization function for programming a memory element Oct 29, 2020 Issued
Array ( [id] => 17107252 [patent_doc_number] => 11127477 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-09-21 [patent_title] => E-fuse circuit [patent_app_type] => utility [patent_app_number] => 17/076827 [patent_app_country] => US [patent_app_date] => 2020-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2835 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17076827 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/076827
E-fuse circuit Oct 21, 2020 Issued
Array ( [id] => 17085216 [patent_doc_number] => 20210280223 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-09 [patent_title] => ON-THE-FLY PROGRAMMING AND VERIFYING METHOD FOR MEMORY CELLS BASED ON COUNTERS AND ECC FEEDBACK [patent_app_type] => utility [patent_app_number] => 17/075502 [patent_app_country] => US [patent_app_date] => 2020-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14829 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17075502 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/075502
On-the-fly programming and verifying method for memory cells based on counters and ECC feedback Oct 19, 2020 Issued
Array ( [id] => 17262393 [patent_doc_number] => 20210375378 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-02 [patent_title] => MEMORY DEVICE AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/065113 [patent_app_country] => US [patent_app_date] => 2020-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8923 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17065113 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/065113
MEMORY DEVICE AND METHOD OF OPERATING THE SAME Oct 6, 2020 Abandoned
Array ( [id] => 17232001 [patent_doc_number] => 20210358558 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-18 [patent_title] => MEMORY DEVICE AND METHOD OF OPERATING THE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/063365 [patent_app_country] => US [patent_app_date] => 2020-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7105 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17063365 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/063365
Memory device and method of generating an internal voltage when an error occurred during standby mode Oct 4, 2020 Issued
Array ( [id] => 17683224 [patent_doc_number] => 11367485 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-21 [patent_title] => CAM storage schemes and CAM read operations for detecting matching keys with bit errors [patent_app_type] => utility [patent_app_number] => 17/036889 [patent_app_country] => US [patent_app_date] => 2020-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 27 [patent_no_of_words] => 60956 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17036889 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/036889
CAM storage schemes and CAM read operations for detecting matching keys with bit errors Sep 28, 2020 Issued
Array ( [id] => 17744257 [patent_doc_number] => 11392324 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-19 [patent_title] => Memory device including interface circuit and method of operating the same [patent_app_type] => utility [patent_app_number] => 17/031069 [patent_app_country] => US [patent_app_date] => 2020-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7238 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17031069 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/031069
Memory device including interface circuit and method of operating the same Sep 23, 2020 Issued
Array ( [id] => 18016143 [patent_doc_number] => 11508446 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-22 [patent_title] => Method for accessing flash memory module and associated flash memory controller and electronic device [patent_app_type] => utility [patent_app_number] => 17/030330 [patent_app_country] => US [patent_app_date] => 2020-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7973 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 277 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17030330 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/030330
Method for accessing flash memory module and associated flash memory controller and electronic device Sep 22, 2020 Issued
Array ( [id] => 16560117 [patent_doc_number] => 20210005266 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-07 [patent_title] => SEMICONDUCTOR MEMORY DEVICE CAPABLE OF REDUCING CHIP SIZE [patent_app_type] => utility [patent_app_number] => 17/023825 [patent_app_country] => US [patent_app_date] => 2020-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5900 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17023825 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/023825
Semiconductor memory device capable of reducing chip size Sep 16, 2020 Issued
Array ( [id] => 17463420 [patent_doc_number] => 20220076726 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-10 [patent_title] => METHODS AND APPARATUS FOR PROBABILISTIC REFRESH IN VOLATILE MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 17/013402 [patent_app_country] => US [patent_app_date] => 2020-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 24934 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17013402 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/013402
METHODS AND APPARATUS FOR PROBABILISTIC REFRESH IN VOLATILE MEMORY DEVICES Sep 3, 2020 Abandoned
Array ( [id] => 17331313 [patent_doc_number] => 11221774 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-11 [patent_title] => Power down mode for universal flash storage (UFS) [patent_app_type] => utility [patent_app_number] => 17/011720 [patent_app_country] => US [patent_app_date] => 2020-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6398 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17011720 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/011720
Power down mode for universal flash storage (UFS) Sep 2, 2020 Issued
Array ( [id] => 17332231 [patent_doc_number] => 11222699 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-11 [patent_title] => Two-part programming methods [patent_app_type] => utility [patent_app_number] => 17/010334 [patent_app_country] => US [patent_app_date] => 2020-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 6197 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17010334 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/010334
Two-part programming methods Sep 1, 2020 Issued
Array ( [id] => 17115346 [patent_doc_number] => 20210295943 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-23 [patent_title] => MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/010041 [patent_app_country] => US [patent_app_date] => 2020-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7631 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17010041 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/010041
Memory system having non-volatile memory Sep 1, 2020 Issued
Array ( [id] => 17825576 [patent_doc_number] => 11430528 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-30 [patent_title] => Determining a read voltage based on a change in a read window [patent_app_type] => utility [patent_app_number] => 17/001757 [patent_app_country] => US [patent_app_date] => 2020-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 9039 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17001757 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/001757
Determining a read voltage based on a change in a read window Aug 24, 2020 Issued
Array ( [id] => 17130067 [patent_doc_number] => 20210304836 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-30 [patent_title] => MULTI-CHIP PACKAGE AND METHOD OF TESTING THE SAME [patent_app_type] => utility [patent_app_number] => 17/000577 [patent_app_country] => US [patent_app_date] => 2020-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5284 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17000577 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/000577
Multi-chip package and method of testing the same Aug 23, 2020 Issued
Array ( [id] => 16487459 [patent_doc_number] => 20200381068 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-03 [patent_title] => MEMORY CONTROLLER, MEMORY DEVICE AND MEMORY SYSTEM HAVING IMPROVED THRESHOLD VOLTAGE DISTRIBUTION CHARACTERISTICS AND RELATED OPERATING METHODS [patent_app_type] => utility [patent_app_number] => 16/999964 [patent_app_country] => US [patent_app_date] => 2020-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13617 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16999964 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/999964
Memory controller, memory device and memory system having improved threshold voltage distribution characteristics and related operating methods Aug 20, 2020 Issued
Array ( [id] => 17326274 [patent_doc_number] => 11217299 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-04 [patent_title] => Device and method for calibrating reference voltage [patent_app_type] => utility [patent_app_number] => 16/997445 [patent_app_country] => US [patent_app_date] => 2020-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 9350 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16997445 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/997445
Device and method for calibrating reference voltage Aug 18, 2020 Issued
Array ( [id] => 17932952 [patent_doc_number] => 20220328078 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-13 [patent_title] => HIERARCHICAL BANK GROUP TIMING [patent_app_type] => utility [patent_app_number] => 17/634370 [patent_app_country] => US [patent_app_date] => 2020-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12187 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17634370 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/634370
Hierarchical bank group timing Aug 12, 2020 Issued
Array ( [id] => 17402658 [patent_doc_number] => 20220044749 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-10 [patent_title] => OVERVOLTAGE PROTECTION FOR CIRCUITS OF MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 16/988285 [patent_app_country] => US [patent_app_date] => 2020-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14951 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16988285 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/988285
Overvoltage protection for circuits of memory devices Aug 6, 2020 Issued
Array ( [id] => 17092667 [patent_doc_number] => 11120860 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-09-14 [patent_title] => Staggering refresh address counters of a number of memory devices, and related methods, devices, and systems [patent_app_type] => utility [patent_app_number] => 16/987168 [patent_app_country] => US [patent_app_date] => 2020-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 9155 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16987168 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/987168
Staggering refresh address counters of a number of memory devices, and related methods, devices, and systems Aug 5, 2020 Issued
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