Search

Kesha Frisby

Examiner (ID: 18159, Phone: (571)272-8774 , Office: P/3715 )

Most Active Art Unit
3715
Art Unit(s)
3714, 3715
Total Applications
954
Issued Applications
470
Pending Applications
70
Abandoned Applications
432

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17590514 [patent_doc_number] => 11328789 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-10 [patent_title] => Intelligent memory device test rack [patent_app_type] => utility [patent_app_number] => 16/719707 [patent_app_country] => US [patent_app_date] => 2019-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11255 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16719707 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/719707
Intelligent memory device test rack Dec 17, 2019 Issued
Array ( [id] => 15775415 [patent_doc_number] => 20200118725 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-16 [patent_title] => SWITCHING OF PERPENDICULARLY MAGNETIZED NANOMAGNETS WITH SPIN-ORBIT TORQUES IN THE ABSENCE OF EXTERNAL MAGNETIC FIELDS [patent_app_type] => utility [patent_app_number] => 16/710531 [patent_app_country] => US [patent_app_date] => 2019-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2611 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16710531 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/710531
Switching of perpendicularly magnetized nanomagnets with spin-orbit torques in the absence of external magnetic fields Dec 10, 2019 Issued
Array ( [id] => 16425091 [patent_doc_number] => 20200350289 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-05 [patent_title] => SEMICONDUCTOR CHIP [patent_app_type] => utility [patent_app_number] => 16/685667 [patent_app_country] => US [patent_app_date] => 2019-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9604 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16685667 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/685667
Semiconductor chip for repairing through electrode Nov 14, 2019 Issued
Array ( [id] => 15938549 [patent_doc_number] => 20200160908 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-21 [patent_title] => DUAL DEMARCATION VOLTAGE SENSING BEFORE WRITES [patent_app_type] => utility [patent_app_number] => 16/685719 [patent_app_country] => US [patent_app_date] => 2019-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7759 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16685719 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/685719
Dual demarcation voltage sensing before writes Nov 14, 2019 Issued
Array ( [id] => 17047807 [patent_doc_number] => 11100997 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-24 [patent_title] => Storage device, controller and method for operating controller for configuring super pages using program timing information [patent_app_type] => utility [patent_app_number] => 16/685405 [patent_app_country] => US [patent_app_date] => 2019-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8560 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16685405 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/685405
Storage device, controller and method for operating controller for configuring super pages using program timing information Nov 14, 2019 Issued
Array ( [id] => 16402061 [patent_doc_number] => 20200342919 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-29 [patent_title] => MEMORY SYSTEM AND METHOD OF OPERATING THE MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 16/679561 [patent_app_country] => US [patent_app_date] => 2019-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11404 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16679561 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/679561
Memory system capable of improving stability of a data read operation of interface circuit, and method of operating the memory system Nov 10, 2019 Issued
Array ( [id] => 15563835 [patent_doc_number] => 20200066329 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-27 [patent_title] => MEMORY SYSTEM AND OPERATION METHOD OF MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 16/669212 [patent_app_country] => US [patent_app_date] => 2019-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8250 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16669212 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/669212
Memory system and operation method of memory system Oct 29, 2019 Issued
Array ( [id] => 16356236 [patent_doc_number] => 10796753 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-10-06 [patent_title] => Method and system to determine quick pass write operation in increment step pulse programming operation [patent_app_type] => utility [patent_app_number] => 16/667653 [patent_app_country] => US [patent_app_date] => 2019-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 4360 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16667653 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/667653
Method and system to determine quick pass write operation in increment step pulse programming operation Oct 28, 2019 Issued
Array ( [id] => 16162699 [patent_doc_number] => 20200219582 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-09 [patent_title] => INTEGRATED CIRCUIT CHIP AND DIE TEST WITHOUT CELL ARRAY [patent_app_type] => utility [patent_app_number] => 16/667738 [patent_app_country] => US [patent_app_date] => 2019-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6042 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16667738 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/667738
Integrated circuit chip and die test without cell array Oct 28, 2019 Issued
Array ( [id] => 16162699 [patent_doc_number] => 20200219582 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-09 [patent_title] => INTEGRATED CIRCUIT CHIP AND DIE TEST WITHOUT CELL ARRAY [patent_app_type] => utility [patent_app_number] => 16/667738 [patent_app_country] => US [patent_app_date] => 2019-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6042 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16667738 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/667738
Integrated circuit chip and die test without cell array Oct 28, 2019 Issued
Array ( [id] => 16162699 [patent_doc_number] => 20200219582 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-09 [patent_title] => INTEGRATED CIRCUIT CHIP AND DIE TEST WITHOUT CELL ARRAY [patent_app_type] => utility [patent_app_number] => 16/667738 [patent_app_country] => US [patent_app_date] => 2019-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6042 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16667738 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/667738
Integrated circuit chip and die test without cell array Oct 28, 2019 Issued
Array ( [id] => 16162699 [patent_doc_number] => 20200219582 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-09 [patent_title] => INTEGRATED CIRCUIT CHIP AND DIE TEST WITHOUT CELL ARRAY [patent_app_type] => utility [patent_app_number] => 16/667738 [patent_app_country] => US [patent_app_date] => 2019-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6042 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16667738 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/667738
Integrated circuit chip and die test without cell array Oct 28, 2019 Issued
Array ( [id] => 15839973 [patent_doc_number] => 20200135269 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-30 [patent_title] => BOOST SCHEMES FOR WRITE ASSIST [patent_app_type] => utility [patent_app_number] => 16/662433 [patent_app_country] => US [patent_app_date] => 2019-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7863 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16662433 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/662433
Boost schemes for write assist Oct 23, 2019 Issued
Array ( [id] => 16668222 [patent_doc_number] => 10937475 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-03-02 [patent_title] => Content addressable memory [patent_app_type] => utility [patent_app_number] => 16/662167 [patent_app_country] => US [patent_app_date] => 2019-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5885 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16662167 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/662167
Content addressable memory Oct 23, 2019 Issued
Array ( [id] => 16394228 [patent_doc_number] => 20200335169 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-22 [patent_title] => MEMORY CONTROLLER, MEMORY DEVICE AND MEMORY SYSTEM HAVING IMPROVED THRESHOLD VOLTAGE DISTRIBUTION CHARACTERISTICS AND RELATED OPERATING METHODS [patent_app_type] => utility [patent_app_number] => 16/661351 [patent_app_country] => US [patent_app_date] => 2019-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11192 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16661351 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/661351
Memory controller, memory device and memory system having improved threshold voltage distribution characteristics and related operating methods Oct 22, 2019 Issued
Array ( [id] => 15502853 [patent_doc_number] => 20200051615 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-13 [patent_title] => MULTI-RANK TOPOLOGY OF MEMORY MODULE AND ASSOCIATED CONTROL METHOD [patent_app_type] => utility [patent_app_number] => 16/658147 [patent_app_country] => US [patent_app_date] => 2019-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3304 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16658147 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/658147
MULTI-RANK TOPOLOGY OF MEMORY MODULE AND ASSOCIATED CONTROL METHOD Oct 19, 2019 Abandoned
Array ( [id] => 16699671 [patent_doc_number] => 10950277 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-03-16 [patent_title] => Signal line layouts including shields, and related methods, devices, and systems [patent_app_type] => utility [patent_app_number] => 16/656907 [patent_app_country] => US [patent_app_date] => 2019-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 8250 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16656907 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/656907
Signal line layouts including shields, and related methods, devices, and systems Oct 17, 2019 Issued
Array ( [id] => 15563837 [patent_doc_number] => 20200066330 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-27 [patent_title] => MEMORY REFRESH TECHNOLOGY AND COMPUTER SYSTEM [patent_app_type] => utility [patent_app_number] => 16/599980 [patent_app_country] => US [patent_app_date] => 2019-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12743 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16599980 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/599980
MEMORY REFRESH TECHNOLOGY AND COMPUTER SYSTEM Oct 10, 2019 Abandoned
Array ( [id] => 15351095 [patent_doc_number] => 20200013439 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-09 [patent_title] => PERFORMING LOGICAL OPERATIONS USING SENSING CIRCUITRY [patent_app_type] => utility [patent_app_number] => 16/576094 [patent_app_country] => US [patent_app_date] => 2019-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 28640 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16576094 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/576094
Performing logical operations using sensing circuitry Sep 18, 2019 Issued
Array ( [id] => 16845760 [patent_doc_number] => 11017854 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-25 [patent_title] => Storage device having a memory cell with a variable resistance element, in which voltage applied to a word line of the memory cell is controlled based on voltage of a bit line of the memory cell [patent_app_type] => utility [patent_app_number] => 16/558905 [patent_app_country] => US [patent_app_date] => 2019-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 7841 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16558905 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/558905
Storage device having a memory cell with a variable resistance element, in which voltage applied to a word line of the memory cell is controlled based on voltage of a bit line of the memory cell Sep 2, 2019 Issued
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