Search

Kesha Frisby

Examiner (ID: 18159, Phone: (571)272-8774 , Office: P/3715 )

Most Active Art Unit
3715
Art Unit(s)
3714, 3715
Total Applications
954
Issued Applications
470
Pending Applications
70
Abandoned Applications
432

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18431444 [patent_doc_number] => 11676671 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-06-13 [patent_title] => Amplification-based read disturb information determination system [patent_app_type] => utility [patent_app_number] => 17/581882 [patent_app_country] => US [patent_app_date] => 2022-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 23360 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17581882 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/581882
Amplification-based read disturb information determination system Jan 21, 2022 Issued
Array ( [id] => 19016102 [patent_doc_number] => 11923042 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-05 [patent_title] => Apparatus, memory device, and method reducing clock training time [patent_app_type] => utility [patent_app_number] => 17/581445 [patent_app_country] => US [patent_app_date] => 2022-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 11838 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17581445 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/581445
Apparatus, memory device, and method reducing clock training time Jan 20, 2022 Issued
Array ( [id] => 18080734 [patent_doc_number] => 20220406346 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-22 [patent_title] => SEMICONDUCTOR CHIP AND VEHICLE COMPRISING THE SAME [patent_app_type] => utility [patent_app_number] => 17/580702 [patent_app_country] => US [patent_app_date] => 2022-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12530 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17580702 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/580702
Semiconductor chip and vehicle comprising the same Jan 20, 2022 Issued
Array ( [id] => 17598220 [patent_doc_number] => 20220147794 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-12 [patent_title] => Deep Learning Neural Network Classifier Using Non-volatile Memory Array [patent_app_type] => utility [patent_app_number] => 17/580862 [patent_app_country] => US [patent_app_date] => 2022-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7907 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17580862 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/580862
Deep learning neural network classifier using non-volatile memory array Jan 20, 2022 Issued
Array ( [id] => 18080732 [patent_doc_number] => 20220406344 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-22 [patent_title] => PROGRAMMABLE COLUMN ACCESS [patent_app_type] => utility [patent_app_number] => 17/648403 [patent_app_country] => US [patent_app_date] => 2022-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15355 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17648403 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/648403
Programmable column access Jan 18, 2022 Issued
Array ( [id] => 18890836 [patent_doc_number] => 11869613 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-09 [patent_title] => Semiconductor structure and endurance test method using the same [patent_app_type] => utility [patent_app_number] => 17/574629 [patent_app_country] => US [patent_app_date] => 2022-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2802 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17574629 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/574629
Semiconductor structure and endurance test method using the same Jan 12, 2022 Issued
Array ( [id] => 20274663 [patent_doc_number] => 12444447 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-14 [patent_title] => Digital phase change memory (PCM) array for analog computing [patent_app_type] => utility [patent_app_number] => 17/565137 [patent_app_country] => US [patent_app_date] => 2021-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3665 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17565137 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/565137
Digital phase change memory (PCM) array for analog computing Dec 28, 2021 Issued
Array ( [id] => 17536462 [patent_doc_number] => 20220115071 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-14 [patent_title] => TWO-PART PROGRAMMING OF MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 17/555728 [patent_app_country] => US [patent_app_date] => 2021-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6212 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17555728 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/555728
Two-part programming of memory cells Dec 19, 2021 Issued
Array ( [id] => 19007421 [patent_doc_number] => 20240071492 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => CONTROL DEVICE, STORAGE DEVICE, SEMICONDUCTOR DEVICE, AND CONTROL METHOD [patent_app_type] => utility [patent_app_number] => 18/270980 [patent_app_country] => US [patent_app_date] => 2021-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9539 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18270980 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/270980
CONTROL DEVICE, STORAGE DEVICE, SEMICONDUCTOR DEVICE, AND CONTROL METHOD Dec 16, 2021 Pending
Array ( [id] => 19494099 [patent_doc_number] => 12112820 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-08 [patent_title] => Single event effect mitigation with smart-redundancy [patent_app_type] => utility [patent_app_number] => 17/539923 [patent_app_country] => US [patent_app_date] => 2021-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9086 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17539923 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/539923
Single event effect mitigation with smart-redundancy Nov 30, 2021 Issued
Array ( [id] => 18804114 [patent_doc_number] => 11837277 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-05 [patent_title] => Dual slc/qlc programming and resource releasing [patent_app_type] => utility [patent_app_number] => 17/455696 [patent_app_country] => US [patent_app_date] => 2021-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5396 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17455696 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/455696
Dual slc/qlc programming and resource releasing Nov 18, 2021 Issued
Array ( [id] => 18857032 [patent_doc_number] => 11854623 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-26 [patent_title] => Memory controller, memory device and memory system having improved threshold voltage distribution characteristics and related operating methods [patent_app_type] => utility [patent_app_number] => 17/520276 [patent_app_country] => US [patent_app_date] => 2021-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 23 [patent_no_of_words] => 11213 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17520276 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/520276
Memory controller, memory device and memory system having improved threshold voltage distribution characteristics and related operating methods Nov 4, 2021 Issued
Array ( [id] => 17900506 [patent_doc_number] => 20220310168 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-29 [patent_title] => OPERATING METHOD OF STORAGE CONTROLLER USING COUNT VALUE OF DIRECT MEMORY ACCESS, STORAGE DEVICE INCLUDING STORAGE CONTROLLER, AND OPERATING METHOD OF STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 17/511738 [patent_app_country] => US [patent_app_date] => 2021-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14427 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17511738 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/511738
OPERATING METHOD OF STORAGE CONTROLLER USING COUNT VALUE OF DIRECT MEMORY ACCESS, STORAGE DEVICE INCLUDING STORAGE CONTROLLER, AND OPERATING METHOD OF STORAGE DEVICE Oct 26, 2021 Abandoned
Array ( [id] => 17752490 [patent_doc_number] => 20220230695 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-21 [patent_title] => NONVOLATILE MEMORY DEVICE, MEMORY SYSTEM INCLUDING SAME, AND OPERATING METHOD OF NONVOLATILE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/498832 [patent_app_country] => US [patent_app_date] => 2021-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9473 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17498832 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/498832
Nonvolatile memory device including artificial neural network, memory system including same, and operating method of nonvolatile memory device including artificial neural network Oct 11, 2021 Issued
Array ( [id] => 18312079 [patent_doc_number] => 20230115979 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-13 [patent_title] => Mitigating Edge Layer Effect In Partially Written Blocks [patent_app_type] => utility [patent_app_number] => 17/499571 [patent_app_country] => US [patent_app_date] => 2021-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5388 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17499571 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/499571
Mitigating edge layer effect in partially written blocks Oct 11, 2021 Issued
Array ( [id] => 18306838 [patent_doc_number] => 20230110738 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-13 [patent_title] => Multibit Memory Device and Method of Operating the Same [patent_app_type] => utility [patent_app_number] => 17/497931 [patent_app_country] => US [patent_app_date] => 2021-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6790 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17497931 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/497931
Multibit memory device and method of operating the same Oct 8, 2021 Issued
Array ( [id] => 18998921 [patent_doc_number] => 11915775 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-27 [patent_title] => Apparatuses and methods for bad row mode [patent_app_type] => utility [patent_app_number] => 17/449297 [patent_app_country] => US [patent_app_date] => 2021-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 8636 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17449297 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/449297
Apparatuses and methods for bad row mode Sep 28, 2021 Issued
Array ( [id] => 18239103 [patent_doc_number] => 20230071414 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-09 [patent_title] => SENSE AMPLIFICATION CIRCUIT AND DATA READING METHOD [patent_app_type] => utility [patent_app_number] => 17/773255 [patent_app_country] => US [patent_app_date] => 2021-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7584 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 401 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17773255 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/773255
SENSE AMPLIFICATION CIRCUIT AND DATA READING METHOD Sep 23, 2021 Abandoned
Array ( [id] => 17318512 [patent_doc_number] => 20210407562 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-30 [patent_title] => PERFORMING LOGICAL OPERATIONS USING SENSING CIRCUITRY [patent_app_type] => utility [patent_app_number] => 17/473615 [patent_app_country] => US [patent_app_date] => 2021-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 28699 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17473615 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/473615
PERFORMING LOGICAL OPERATIONS USING SENSING CIRCUITRY Sep 12, 2021 Abandoned
Array ( [id] => 18688131 [patent_doc_number] => 11783874 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-10 [patent_title] => Memory with swap mode [patent_app_type] => utility [patent_app_number] => 17/470579 [patent_app_country] => US [patent_app_date] => 2021-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 11030 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17470579 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/470579
Memory with swap mode Sep 8, 2021 Issued
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