Search

Kesha Frisby

Examiner (ID: 18159, Phone: (571)272-8774 , Office: P/3715 )

Most Active Art Unit
3715
Art Unit(s)
3714, 3715
Total Applications
954
Issued Applications
470
Pending Applications
70
Abandoned Applications
432

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18131145 [patent_doc_number] => 11557360 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-01-17 [patent_title] => Memory test circuit and device wafer [patent_app_type] => utility [patent_app_number] => 17/467878 [patent_app_country] => US [patent_app_date] => 2021-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8973 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17467878 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/467878
Memory test circuit and device wafer Sep 6, 2021 Issued
Array ( [id] => 18721293 [patent_doc_number] => 11798645 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-24 [patent_title] => Storage device for performing reliability check by using error correction code (ECC) data [patent_app_type] => utility [patent_app_number] => 17/467968 [patent_app_country] => US [patent_app_date] => 2021-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 11036 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17467968 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/467968
Storage device for performing reliability check by using error correction code (ECC) data Sep 6, 2021 Issued
Array ( [id] => 18548049 [patent_doc_number] => 11721407 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-08 [patent_title] => BIST for performing parallel and serial test on memories [patent_app_type] => utility [patent_app_number] => 17/463937 [patent_app_country] => US [patent_app_date] => 2021-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 8697 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17463937 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/463937
BIST for performing parallel and serial test on memories Aug 31, 2021 Issued
Array ( [id] => 17401668 [patent_doc_number] => 20220043758 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-10 [patent_title] => LOW LATENCY MEMORY ACCESS [patent_app_type] => utility [patent_app_number] => 17/461064 [patent_app_country] => US [patent_app_date] => 2021-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10348 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17461064 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/461064
Low latency memory access Aug 29, 2021 Issued
Array ( [id] => 17886173 [patent_doc_number] => 20220301650 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-22 [patent_title] => CONTROLLER CONTROLLING SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE CONTROLLER [patent_app_type] => utility [patent_app_number] => 17/461749 [patent_app_country] => US [patent_app_date] => 2021-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13602 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17461749 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/461749
CONTROLLER CONTROLLING SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE CONTROLLER Aug 29, 2021 Abandoned
Array ( [id] => 18235788 [patent_doc_number] => 11600352 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-07 [patent_title] => Storage device [patent_app_type] => utility [patent_app_number] => 17/459807 [patent_app_country] => US [patent_app_date] => 2021-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 8327 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17459807 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/459807
Storage device Aug 26, 2021 Issued
Array ( [id] => 17447828 [patent_doc_number] => 20220068333 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => MEMORY [patent_app_type] => utility [patent_app_number] => 17/409915 [patent_app_country] => US [patent_app_date] => 2021-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7539 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17409915 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/409915
Memory devices operating on different states of clock signal Aug 23, 2021 Issued
Array ( [id] => 17485701 [patent_doc_number] => 20220093205 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => METHOD FOR EVALUATING PERFORMANCE OF INTERFACE CIRCUIT AND RELATED DEVICE [patent_app_type] => utility [patent_app_number] => 17/445605 [patent_app_country] => US [patent_app_date] => 2021-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9221 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17445605 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/445605
METHOD FOR EVALUATING PERFORMANCE OF INTERFACE CIRCUIT AND RELATED DEVICE Aug 21, 2021 Abandoned
Array ( [id] => 18211448 [patent_doc_number] => 20230057711 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-23 [patent_title] => SYSTEM AND METHOD FOR DYNAMIC INTER-CELL INTERFERENCE COMPENSATION IN NON-VOLATILE MEMORY STORAGE DEVICES [patent_app_type] => utility [patent_app_number] => 17/406929 [patent_app_country] => US [patent_app_date] => 2021-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14583 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17406929 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/406929
SYSTEM AND METHOD FOR DYNAMIC INTER-CELL INTERFERENCE COMPENSATION IN NON-VOLATILE MEMORY STORAGE DEVICES Aug 18, 2021 Pending
Array ( [id] => 17276636 [patent_doc_number] => 20210382834 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-09 [patent_title] => MEMORY MODULE WITH DATA BUFFERING [patent_app_type] => utility [patent_app_number] => 17/403832 [patent_app_country] => US [patent_app_date] => 2021-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19949 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 526 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17403832 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/403832
Memory module with data buffering Aug 15, 2021 Issued
Array ( [id] => 18292175 [patent_doc_number] => 11621048 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-04 [patent_title] => Positioning read thresholds in a nonvolatile memory based on successful decoding [patent_app_type] => utility [patent_app_number] => 17/388048 [patent_app_country] => US [patent_app_date] => 2021-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7064 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17388048 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/388048
Positioning read thresholds in a nonvolatile memory based on successful decoding Jul 28, 2021 Issued
Array ( [id] => 18935211 [patent_doc_number] => 11887649 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-30 [patent_title] => Staggering refresh address counters of a number of memory devices, and related methods, devices, and systems [patent_app_type] => utility [patent_app_number] => 17/387428 [patent_app_country] => US [patent_app_date] => 2021-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 9199 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17387428 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/387428
Staggering refresh address counters of a number of memory devices, and related methods, devices, and systems Jul 27, 2021 Issued
Array ( [id] => 18494072 [patent_doc_number] => 11699493 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-11 [patent_title] => Method and apparatus for performing a read of a flash memory using predicted retention-and-read-disturb-compensated threshold voltage shift offset values [patent_app_type] => utility [patent_app_number] => 17/385857 [patent_app_country] => US [patent_app_date] => 2021-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7216 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17385857 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/385857
Method and apparatus for performing a read of a flash memory using predicted retention-and-read-disturb-compensated threshold voltage shift offset values Jul 25, 2021 Issued
Array ( [id] => 17582619 [patent_doc_number] => 20220139474 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => MEMORY CONTROLLER, MEMORY SYSTEM WITH IMPROVED THRESHOLD VOLTAGE DISTRIBUTION CHARACTERISTICS, AND OPERATION METHOD [patent_app_type] => utility [patent_app_number] => 17/384219 [patent_app_country] => US [patent_app_date] => 2021-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8960 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17384219 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/384219
Memory controller, memory system with improved threshold voltage distribution characteristics, and operation method Jul 22, 2021 Issued
Array ( [id] => 17416840 [patent_doc_number] => 20220051744 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-17 [patent_title] => MEMORY CONTROLLER WITH ADAPTIVE REFRESH RATE CONTROLLED BY ERROR BIT INFORMATION [patent_app_type] => utility [patent_app_number] => 17/377350 [patent_app_country] => US [patent_app_date] => 2021-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2152 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17377350 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/377350
MEMORY CONTROLLER WITH ADAPTIVE REFRESH RATE CONTROLLED BY ERROR BIT INFORMATION Jul 14, 2021 Abandoned
Array ( [id] => 19356699 [patent_doc_number] => 12057154 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-06 [patent_title] => Method for efficiently waking up ferroelectric memory [patent_app_type] => utility [patent_app_number] => 17/370144 [patent_app_country] => US [patent_app_date] => 2021-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 38 [patent_no_of_words] => 11072 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17370144 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/370144
Method for efficiently waking up ferroelectric memory Jul 7, 2021 Issued
Array ( [id] => 17188537 [patent_doc_number] => 20210335422 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-28 [patent_title] => METHOD OF OPERATING RESISTIVE MEMORY DEVICE TO INCREASE READ MARGIN [patent_app_type] => utility [patent_app_number] => 17/369211 [patent_app_country] => US [patent_app_date] => 2021-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13671 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17369211 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/369211
Method of operating resistive memory device to increase read margin Jul 6, 2021 Issued
Array ( [id] => 17508827 [patent_doc_number] => 20220101930 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => NONVOLATILE MEMORY DEVICE AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/359688 [patent_app_country] => US [patent_app_date] => 2021-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15689 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17359688 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/359688
Nonvolatile memory device and operation method of detecting defective memory cells Jun 27, 2021 Issued
Array ( [id] => 18528516 [patent_doc_number] => 11715514 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-01 [patent_title] => Latch bit cells [patent_app_type] => utility [patent_app_number] => 17/359209 [patent_app_country] => US [patent_app_date] => 2021-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 4512 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17359209 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/359209
Latch bit cells Jun 24, 2021 Issued
Array ( [id] => 17173804 [patent_doc_number] => 20210327475 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-21 [patent_title] => Configuring a Host Interface of a Memory Device Based on Mode of Operation [patent_app_type] => utility [patent_app_number] => 17/356431 [patent_app_country] => US [patent_app_date] => 2021-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7778 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17356431 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/356431
Configuring a host interface of a memory device based on mode of operation Jun 22, 2021 Issued
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