Ket D. Dang

Array ( [id] => 3745013 [patent_doc_number] => 05716867 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-10 [patent_title] => 'Solid state image sensor' [patent_app_type] => 1 [patent_app_number] => 8/694703 [patent_app_country] => US [patent_app_date] => 1996-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3570 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/716/05716867.pdf [firstpage_image] =>[orig_patent_app_number] => 694703 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3826549 [patent_doc_number] => 05711814 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-27 [patent_title] => 'Method of and apparatus for forming film with rotary electrode' [patent_app_type] => 1 [patent_app_number] => 8/691027 [patent_app_country] => US [patent_app_date] => 1996-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 20 [patent_no_of_words] => 9398 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/711/05711814.pdf [firstpage_image] =>[orig_patent_app_number] => 691027 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3858685 [patent_doc_number] => 05792687 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-11 [patent_title] => 'Method for fabricating high density integrated circuits using oxide and polysilicon spacers' [patent_app_type] => 1 [patent_app_number] => 8/691289 [patent_app_country] => US [patent_app_date] => 1996-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 4383 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 310 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/792/05792687.pdf [firstpage_image] =>[orig_patent_app_number] => 691289 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3680048 [patent_doc_number] => 05643365 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-01 [patent_title] => 'Method and device for plasma vapor chemical deposition of homogeneous films on large flat surfaces' [patent_app_type] => 1 [patent_app_number] => 8/686464 [patent_app_country] => US [patent_app_date] => 1996-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3919 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/643/05643365.pdf [firstpage_image] =>[orig_patent_app_number] => 686464 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3813243 [patent_doc_number] => 05789277 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-04 [patent_title] => 'Method of making chalogenide memory device' [patent_app_type] => 1 [patent_app_number] => 8/686493 [patent_app_country] => US [patent_app_date] => 1996-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 48 [patent_no_of_words] => 9569 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/789/05789277.pdf [firstpage_image] =>[orig_patent_app_number] => 686493 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3876960 [patent_doc_number] => 05728615 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-17 [patent_title] => 'Method of manufacturing a polysilicon resistor having uniform resistance' [patent_app_type] => 1 [patent_app_number] => 8/683367 [patent_app_country] => US [patent_app_date] => 1996-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 3066 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/728/05728615.pdf [firstpage_image] =>[orig_patent_app_number] => 683367 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4002723 [patent_doc_number] => 06004844 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-21 [patent_title] => 'Unit cell layout and transfer gate design for high density DRAMs' [patent_app_type] => 1 [patent_app_number] => 8/680765 [patent_app_country] => US [patent_app_date] => 1996-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 4502 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/004/06004844.pdf [firstpage_image] =>[orig_patent_app_number] => 680765 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3834590 [patent_doc_number] => 05707452 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-13 [patent_title] => 'Coaxial microwave applicator for an electron cyclotron resonance plasma source' [patent_app_type] => 1 [patent_app_number] => 8/676448 [patent_app_country] => US [patent_app_date] => 1996-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 7299 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/707/05707452.pdf [firstpage_image] =>[orig_patent_app_number] => 676448 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3614338 [patent_doc_number] => 05688331 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-18 [patent_title] => 'Resistance heated stem mounted aluminum susceptor assembly' [patent_app_type] => 1 [patent_app_number] => 8/673599 [patent_app_country] => US [patent_app_date] => 1996-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 23 [patent_no_of_words] => 6745 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/688/05688331.pdf [firstpage_image] =>[orig_patent_app_number] => 673599 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3694095 [patent_doc_number] => 05645645 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-08 [patent_title] => 'Method and apparatus for plasma treatment of a surface' [patent_app_type] => 1 [patent_app_number] => 8/672456 [patent_app_country] => US [patent_app_date] => 1996-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 4478 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/645/05645645.pdf [firstpage_image] =>[orig_patent_app_number] => 672456 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3726826 [patent_doc_number] => 05702970 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-30 [patent_title] => 'Method for fabricating a capacitor of a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/670592 [patent_app_country] => US [patent_app_date] => 1996-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 22 [patent_no_of_words] => 4849 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/702/05702970.pdf [firstpage_image] =>[orig_patent_app_number] => 670592 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3697525 [patent_doc_number] => 05677249 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-14 [patent_title] => 'Semiconductor apparatus and production method for the same' [patent_app_type] => 1 [patent_app_number] => 8/670927 [patent_app_country] => US [patent_app_date] => 1996-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 38 [patent_no_of_words] => 10285 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/677/05677249.pdf [firstpage_image] =>[orig_patent_app_number] => 670927 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3824545 [patent_doc_number] => 05731234 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-24 [patent_title] => 'Process for global planarization of memory and globally planarized memory' [patent_app_type] => 1 [patent_app_number] => 8/669965 [patent_app_country] => US [patent_app_date] => 1996-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 2096 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/731/05731234.pdf [firstpage_image] =>[orig_patent_app_number] => 669965 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3771698 [patent_doc_number] => 05807775 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-15 [patent_title] => 'Method for forming a double walled cylindrical capacitor for a DRAM' [patent_app_type] => 1 [patent_app_number] => 8/668713 [patent_app_country] => US [patent_app_date] => 1996-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 2981 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 299 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/807/05807775.pdf [firstpage_image] =>[orig_patent_app_number] => 668713 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3663369 [patent_doc_number] => 05668036 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-16 [patent_title] => 'Fabrication method of the post structure of the cell for high density DRAM' [patent_app_type] => 1 [patent_app_number] => 8/667695 [patent_app_country] => US [patent_app_date] => 1996-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 3684 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 17 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/668/05668036.pdf [firstpage_image] =>[orig_patent_app_number] => 667695 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3726920 [patent_doc_number] => 05670404 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-23 [patent_title] => 'Method for making self-aligned bit line contacts on a DRAM circuit having a planarized insulating layer' [patent_app_type] => 1 [patent_app_number] => 8/667697 [patent_app_country] => US [patent_app_date] => 1996-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4714 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 343 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/670/05670404.pdf [firstpage_image] =>[orig_patent_app_number] => 667697 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3697082 [patent_doc_number] => 05677221 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-14 [patent_title] => 'Method of manufacture DRAM capacitor with reduced layout area' [patent_app_type] => 1 [patent_app_number] => 8/666801 [patent_app_country] => US [patent_app_date] => 1996-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2409 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/677/05677221.pdf [firstpage_image] =>[orig_patent_app_number] => 666801 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3813420 [patent_doc_number] => 05789289 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-04 [patent_title] => 'Method for fabricating vertical fin capacitor structures' [patent_app_type] => 1 [patent_app_number] => 8/665601 [patent_app_country] => US [patent_app_date] => 1996-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 22 [patent_no_of_words] => 4928 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/789/05789289.pdf [firstpage_image] =>[orig_patent_app_number] => 665601 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3663355 [patent_doc_number] => 05668035 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-16 [patent_title] => 'Method for fabricating a dual-gate dielectric module for memory with embedded logic technology' [patent_app_type] => 1 [patent_app_number] => 8/661259 [patent_app_country] => US [patent_app_date] => 1996-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 2988 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 301 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/668/05668035.pdf [firstpage_image] =>[orig_patent_app_number] => 661259 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3735729 [patent_doc_number] => 05800619 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-01 [patent_title] => 'Vacuum plasma processor having coil with minimum magnetic field in its center' [patent_app_type] => 1 [patent_app_number] => 8/661203 [patent_app_country] => US [patent_app_date] => 1996-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 8740 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/800/05800619.pdf [firstpage_image] =>[orig_patent_app_number] => 661203 [rel_patent_id] =>[rel_patent_doc_number] =>)