Search

Ket D. Dang

Examiner (ID: 18985, Phone: (571)270-7827 , Office: P/3742 )

Most Active Art Unit
3742
Art Unit(s)
3742, 3761
Total Applications
696
Issued Applications
407
Pending Applications
43
Abandoned Applications
258

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3869923 [patent_doc_number] => 05763306 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-09 [patent_title] => 'Method of fabricating capacitor over bit line COB structure for a very high density DRAM applications' [patent_app_type] => 1 [patent_app_number] => 8/957675 [patent_app_country] => US [patent_app_date] => 1997-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 3785 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 411 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/763/05763306.pdf [firstpage_image] =>[orig_patent_app_number] => 957675 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/957675
Method of fabricating capacitor over bit line COB structure for a very high density DRAM applications Oct 23, 1997 Issued
Array ( [id] => 4006684 [patent_doc_number] => 05888864 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-30 [patent_title] => 'Manufacturing method of DRAM Cell formed on an insulating layer having a vertical channel' [patent_app_type] => 1 [patent_app_number] => 8/955157 [patent_app_country] => US [patent_app_date] => 1997-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2171 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 319 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/888/05888864.pdf [firstpage_image] =>[orig_patent_app_number] => 955157 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/955157
Manufacturing method of DRAM Cell formed on an insulating layer having a vertical channel Oct 20, 1997 Issued
Array ( [id] => 4062748 [patent_doc_number] => 05866455 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-02 [patent_title] => 'Method for forming a dram cell with a multiple pillar-shaped capacitor' [patent_app_type] => 1 [patent_app_number] => 8/954413 [patent_app_country] => US [patent_app_date] => 1997-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 1847 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/866/05866455.pdf [firstpage_image] =>[orig_patent_app_number] => 954413 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/954413
Method for forming a dram cell with a multiple pillar-shaped capacitor Oct 19, 1997 Issued
Array ( [id] => 3826270 [patent_doc_number] => 05759895 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-02 [patent_title] => 'Method of fabricating a capacitor storage node having a rugged-fin surface' [patent_app_type] => 1 [patent_app_number] => 8/949469 [patent_app_country] => US [patent_app_date] => 1997-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 2326 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 289 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/759/05759895.pdf [firstpage_image] =>[orig_patent_app_number] => 949469 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/949469
Method of fabricating a capacitor storage node having a rugged-fin surface Oct 13, 1997 Issued
Array ( [id] => 3797102 [patent_doc_number] => 05827764 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-27 [patent_title] => 'Method for reducing the contact resistance of a butt contact' [patent_app_type] => 1 [patent_app_number] => 8/947833 [patent_app_country] => US [patent_app_date] => 1997-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 3265 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 291 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/827/05827764.pdf [firstpage_image] =>[orig_patent_app_number] => 947833 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/947833
Method for reducing the contact resistance of a butt contact Oct 7, 1997 Issued
Array ( [id] => 3923794 [patent_doc_number] => 05945353 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-31 [patent_title] => 'Plasma processing method' [patent_app_type] => 1 [patent_app_number] => 8/942119 [patent_app_country] => US [patent_app_date] => 1997-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 7822 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/945/05945353.pdf [firstpage_image] =>[orig_patent_app_number] => 942119 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/942119
Plasma processing method Sep 30, 1997 Issued
Array ( [id] => 4085457 [patent_doc_number] => 06017788 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-25 [patent_title] => 'Method of fabricating bit line' [patent_app_type] => 1 [patent_app_number] => 8/941085 [patent_app_country] => US [patent_app_date] => 1997-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 1620 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/017/06017788.pdf [firstpage_image] =>[orig_patent_app_number] => 941085 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/941085
Method of fabricating bit line Sep 29, 1997 Issued
Array ( [id] => 3759617 [patent_doc_number] => 05843820 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-01 [patent_title] => 'Method of fabricating a new dynamic random access memory (DRAM) cell having a buried horizontal trench capacitor' [patent_app_type] => 1 [patent_app_number] => 8/939971 [patent_app_country] => US [patent_app_date] => 1997-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 6363 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/843/05843820.pdf [firstpage_image] =>[orig_patent_app_number] => 939971 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/939971
Method of fabricating a new dynamic random access memory (DRAM) cell having a buried horizontal trench capacitor Sep 28, 1997 Issued
Array ( [id] => 3941395 [patent_doc_number] => 05989948 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-23 [patent_title] => 'Methods of forming pairs of transistors, and methods of forming pairs of transistors having different voltage tolerances' [patent_app_type] => 1 [patent_app_number] => 8/934831 [patent_app_country] => US [patent_app_date] => 1997-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2802 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/989/05989948.pdf [firstpage_image] =>[orig_patent_app_number] => 934831 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/934831
Methods of forming pairs of transistors, and methods of forming pairs of transistors having different voltage tolerances Sep 21, 1997 Issued
Array ( [id] => 4046419 [patent_doc_number] => 05869368 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-09 [patent_title] => 'Method to increase capacitance' [patent_app_type] => 1 [patent_app_number] => 8/934785 [patent_app_country] => US [patent_app_date] => 1997-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 4095 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/869/05869368.pdf [firstpage_image] =>[orig_patent_app_number] => 934785 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/934785
Method to increase capacitance Sep 21, 1997 Issued
Array ( [id] => 3759558 [patent_doc_number] => 05843817 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-01 [patent_title] => 'Process for integrating stacked capacitor DRAM devices with MOSFET devices used for high performance logic circuits' [patent_app_type] => 1 [patent_app_number] => 8/933371 [patent_app_country] => US [patent_app_date] => 1997-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3017 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 423 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/843/05843817.pdf [firstpage_image] =>[orig_patent_app_number] => 933371 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/933371
Process for integrating stacked capacitor DRAM devices with MOSFET devices used for high performance logic circuits Sep 18, 1997 Issued
Array ( [id] => 3944868 [patent_doc_number] => 05953576 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-14 [patent_title] => 'Method for fabricating a capacitor of a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/925060 [patent_app_country] => US [patent_app_date] => 1997-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 22 [patent_no_of_words] => 4856 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/953/05953576.pdf [firstpage_image] =>[orig_patent_app_number] => 925060 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/925060
Method for fabricating a capacitor of a semiconductor device Sep 8, 1997 Issued
Array ( [id] => 3937522 [patent_doc_number] => 05981352 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Consistent alignment mark profiles on semiconductor wafers using fine grain tungsten protective layer' [patent_app_type] => 1 [patent_app_number] => 8/924903 [patent_app_country] => US [patent_app_date] => 1997-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 3515 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/981/05981352.pdf [firstpage_image] =>[orig_patent_app_number] => 924903 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/924903
Consistent alignment mark profiles on semiconductor wafers using fine grain tungsten protective layer Sep 7, 1997 Issued
Array ( [id] => 3806040 [patent_doc_number] => 05854102 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-29 [patent_title] => 'Vertical diode structures with low series resistance' [patent_app_type] => 1 [patent_app_number] => 8/932791 [patent_app_country] => US [patent_app_date] => 1997-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 35 [patent_no_of_words] => 9175 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/854/05854102.pdf [firstpage_image] =>[orig_patent_app_number] => 932791 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/932791
Vertical diode structures with low series resistance Sep 4, 1997 Issued
Array ( [id] => 3806108 [patent_doc_number] => 05854107 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-29 [patent_title] => 'Method for forming capacitor of semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/924843 [patent_app_country] => US [patent_app_date] => 1997-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 3318 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/854/05854107.pdf [firstpage_image] =>[orig_patent_app_number] => 924843 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/924843
Method for forming capacitor of semiconductor device Sep 4, 1997 Issued
Array ( [id] => 3967010 [patent_doc_number] => 05956589 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-21 [patent_title] => 'Method of forming narrow thermal silicon dioxide side isolation regions in a semiconductor substrate and MOS semiconductor devices fabricated by this method' [patent_app_type] => 1 [patent_app_number] => 8/924861 [patent_app_country] => US [patent_app_date] => 1997-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 2232 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/956/05956589.pdf [firstpage_image] =>[orig_patent_app_number] => 924861 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/924861
Method of forming narrow thermal silicon dioxide side isolation regions in a semiconductor substrate and MOS semiconductor devices fabricated by this method Sep 4, 1997 Issued
Array ( [id] => 4029372 [patent_doc_number] => 05994180 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'Method of making SRAM having part of load resistance layer functions as power supply line' [patent_app_type] => 1 [patent_app_number] => 8/917823 [patent_app_country] => US [patent_app_date] => 1997-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 66 [patent_no_of_words] => 9999 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/994/05994180.pdf [firstpage_image] =>[orig_patent_app_number] => 917823 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/917823
Method of making SRAM having part of load resistance layer functions as power supply line Aug 26, 1997 Issued
Array ( [id] => 3858751 [patent_doc_number] => 05792692 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-11 [patent_title] => 'Method of fabricating a twin hammer tree shaped capacitor structure for a dram device' [patent_app_type] => 1 [patent_app_number] => 8/912323 [patent_app_country] => US [patent_app_date] => 1997-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 25 [patent_no_of_words] => 3802 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 382 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/792/05792692.pdf [firstpage_image] =>[orig_patent_app_number] => 912323 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/912323
Method of fabricating a twin hammer tree shaped capacitor structure for a dram device Aug 17, 1997 Issued
Array ( [id] => 3806159 [patent_doc_number] => 05854111 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-29 [patent_title] => 'ROM device using a schuckly diode' [patent_app_type] => 1 [patent_app_number] => 8/906313 [patent_app_country] => US [patent_app_date] => 1997-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 24 [patent_no_of_words] => 2933 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 289 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/854/05854111.pdf [firstpage_image] =>[orig_patent_app_number] => 906313 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/906313
ROM device using a schuckly diode Aug 4, 1997 Issued
Array ( [id] => 3807947 [patent_doc_number] => 05811330 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-22 [patent_title] => 'Method of fabricating an overvoltage protection device in integrated circuits' [patent_app_type] => 1 [patent_app_number] => 8/901946 [patent_app_country] => US [patent_app_date] => 1997-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 4156 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 301 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/811/05811330.pdf [firstpage_image] =>[orig_patent_app_number] => 901946 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/901946
Method of fabricating an overvoltage protection device in integrated circuits Jul 28, 1997 Issued
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