
Ket D. Dang
Examiner (ID: 18985, Phone: (571)270-7827 , Office: P/3742 )
| Most Active Art Unit | 3742 |
| Art Unit(s) | 3742, 3761 |
| Total Applications | 696 |
| Issued Applications | 407 |
| Pending Applications | 43 |
| Abandoned Applications | 258 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3942263
[patent_doc_number] => 05946577
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-08-31
[patent_title] => 'Method of manufacturing semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 8/900615
[patent_app_country] => US
[patent_app_date] => 1997-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 11
[patent_no_of_words] => 2348
[patent_no_of_claims] => 10
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[patent_words_short_claim] => 159
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/946/05946577.pdf
[firstpage_image] =>[orig_patent_app_number] => 900615
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/900615 | Method of manufacturing semiconductor device | Jul 24, 1997 | Issued |
Array
(
[id] => 3937228
[patent_doc_number] => 05981331
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-09
[patent_title] => 'Method of manufacturing a semiconductor memory device with a high dielectric constant capacitor'
[patent_app_type] => 1
[patent_app_number] => 8/901245
[patent_app_country] => US
[patent_app_date] => 1997-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
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[patent_no_of_words] => 7249
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/981/05981331.pdf
[firstpage_image] =>[orig_patent_app_number] => 901245
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/901245 | Method of manufacturing a semiconductor memory device with a high dielectric constant capacitor | Jul 24, 1997 | Issued |
| 08/899099 | STRUCTURE AND FABRICATION METHOD FOR NON-PLANAR MEMORY ELEMENTS | Jul 23, 1997 | Abandoned |
Array
(
[id] => 4006836
[patent_doc_number] => 05888875
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-03-30
[patent_title] => 'Diffusion resistor structure with silicided contact areas, and methods of fabrication thereof'
[patent_app_type] => 1
[patent_app_number] => 8/898264
[patent_app_country] => US
[patent_app_date] => 1997-07-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[patent_no_of_words] => 3872
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[pdf_file] => patents/05/888/05888875.pdf
[firstpage_image] =>[orig_patent_app_number] => 898264
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/898264 | Diffusion resistor structure with silicided contact areas, and methods of fabrication thereof | Jul 21, 1997 | Issued |
Array
(
[id] => 4206556
[patent_doc_number] => 06027971
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-22
[patent_title] => 'Methods of forming memory devices having protected gate electrodes'
[patent_app_type] => 1
[patent_app_number] => 8/895513
[patent_app_country] => US
[patent_app_date] => 1997-07-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
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[patent_no_of_words] => 5576
[patent_no_of_claims] => 30
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/027/06027971.pdf
[firstpage_image] =>[orig_patent_app_number] => 895513
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/895513 | Methods of forming memory devices having protected gate electrodes | Jul 15, 1997 | Issued |
Array
(
[id] => 3867482
[patent_doc_number] => 05837578
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-11-17
[patent_title] => 'Process of manufacturing a trenched stack-capacitor'
[patent_app_type] => 1
[patent_app_number] => 8/895107
[patent_app_country] => US
[patent_app_date] => 1997-07-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
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[patent_no_of_words] => 3758
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[pdf_file] => patents/05/837/05837578.pdf
[firstpage_image] =>[orig_patent_app_number] => 895107
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/895107 | Process of manufacturing a trenched stack-capacitor | Jul 15, 1997 | Issued |
Array
(
[id] => 3740564
[patent_doc_number] => 05786253
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-07-28
[patent_title] => 'Method of making a multi-level ROM device'
[patent_app_type] => 1
[patent_app_number] => 8/892025
[patent_app_country] => US
[patent_app_date] => 1997-07-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 2162
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[pdf_file] => patents/05/786/05786253.pdf
[firstpage_image] =>[orig_patent_app_number] => 892025
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/892025 | Method of making a multi-level ROM device | Jul 13, 1997 | Issued |
Array
(
[id] => 3964916
[patent_doc_number] => 05885875
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-03-23
[patent_title] => 'Low voltage electro-static discharge protective device and method of fabricating the same'
[patent_app_type] => 1
[patent_app_number] => 8/892023
[patent_app_country] => US
[patent_app_date] => 1997-07-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 1345
[patent_no_of_claims] => 5
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/885/05885875.pdf
[firstpage_image] =>[orig_patent_app_number] => 892023
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/892023 | Low voltage electro-static discharge protective device and method of fabricating the same | Jul 13, 1997 | Issued |
Array
(
[id] => 3952892
[patent_doc_number] => 05940704
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-08-17
[patent_title] => 'Method of manufacturing a reference apparatus'
[patent_app_type] => 1
[patent_app_number] => 8/890440
[patent_app_country] => US
[patent_app_date] => 1997-07-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 18
[patent_no_of_words] => 6013
[patent_no_of_claims] => 2
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/940/05940704.pdf
[firstpage_image] =>[orig_patent_app_number] => 890440
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/890440 | Method of manufacturing a reference apparatus | Jul 8, 1997 | Issued |
Array
(
[id] => 4108318
[patent_doc_number] => 06051855
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-04-18
[patent_title] => 'Electrostatic capacitive sensor'
[patent_app_type] => 1
[patent_app_number] => 8/886433
[patent_app_country] => US
[patent_app_date] => 1997-07-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[pdf_file] => patents/06/051/06051855.pdf
[firstpage_image] =>[orig_patent_app_number] => 886433
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/886433 | Electrostatic capacitive sensor | Jul 1, 1997 | Issued |
Array
(
[id] => 3994261
[patent_doc_number] => 05985756
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-16
[patent_title] => 'Method of forming an interconnection in a contact hole in an insulation layer over a silicon substrate'
[patent_app_type] => 1
[patent_app_number] => 8/884035
[patent_app_country] => US
[patent_app_date] => 1997-06-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[pdf_file] => patents/05/985/05985756.pdf
[firstpage_image] =>[orig_patent_app_number] => 884035
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/884035 | Method of forming an interconnection in a contact hole in an insulation layer over a silicon substrate | Jun 26, 1997 | Issued |
Array
(
[id] => 3936867
[patent_doc_number] => 05915175
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-06-22
[patent_title] => 'Mitigation of CMP-induced BPSG surface damage by an integrated anneal and silicon dioxide deposition'
[patent_app_type] => 1
[patent_app_number] => 8/884119
[patent_app_country] => US
[patent_app_date] => 1997-06-27
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/915/05915175.pdf
[firstpage_image] =>[orig_patent_app_number] => 884119
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/884119 | Mitigation of CMP-induced BPSG surface damage by an integrated anneal and silicon dioxide deposition | Jun 26, 1997 | Issued |
Array
(
[id] => 3768795
[patent_doc_number] => 05849617
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-12-15
[patent_title] => 'Method for fabricating a nested capacitor'
[patent_app_type] => 1
[patent_app_number] => 8/881753
[patent_app_country] => US
[patent_app_date] => 1997-06-24
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[pdf_file] => patents/05/849/05849617.pdf
[firstpage_image] =>[orig_patent_app_number] => 881753
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/881753 | Method for fabricating a nested capacitor | Jun 23, 1997 | Issued |
Array
(
[id] => 3858742
[patent_doc_number] => 05792691
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-08-11
[patent_title] => 'Method of manufacturing semiconductor memory device having a capacitor'
[patent_app_type] => 1
[patent_app_number] => 8/881493
[patent_app_country] => US
[patent_app_date] => 1997-06-24
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[pdf_file] => patents/05/792/05792691.pdf
[firstpage_image] =>[orig_patent_app_number] => 881493
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/881493 | Method of manufacturing semiconductor memory device having a capacitor | Jun 23, 1997 | Issued |
Array
(
[id] => 3942082
[patent_doc_number] => 05946565
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-08-31
[patent_title] => 'Semiconductor integrated circuit device and process for manufacturing the same'
[patent_app_type] => 1
[patent_app_number] => 8/880736
[patent_app_country] => US
[patent_app_date] => 1997-06-23
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/946/05946565.pdf
[firstpage_image] =>[orig_patent_app_number] => 880736
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/880736 | Semiconductor integrated circuit device and process for manufacturing the same | Jun 22, 1997 | Issued |
Array
(
[id] => 4042234
[patent_doc_number] => 05874336
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-02-23
[patent_title] => 'Method to improve yield for capacitors formed using etchback of polysilicon hemispherical grains'
[patent_app_type] => 1
[patent_app_number] => 8/880953
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[pdf_file] => patents/05/874/05874336.pdf
[firstpage_image] =>[orig_patent_app_number] => 880953
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/880953 | Method to improve yield for capacitors formed using etchback of polysilicon hemispherical grains | Jun 22, 1997 | Issued |
Array
(
[id] => 4107349
[patent_doc_number] => 06057190
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[patent_title] => 'Method of manufacturing semiconductor device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/880989 | Method of manufacturing semiconductor device | Jun 22, 1997 | Issued |
Array
(
[id] => 4011725
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/878815 | Method for manufacturing a capacitor | Jun 18, 1997 | Issued |
Array
(
[id] => 3785847
[patent_doc_number] => 05840596
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[patent_kind] => NA
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[patent_title] => 'Method of manufacturing complementary modulation-doped field effect transistors'
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[firstpage_image] =>[orig_patent_app_number] => 874253
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/874253 | Method of manufacturing complementary modulation-doped field effect transistors | Jun 12, 1997 | Issued |
Array
(
[id] => 3804574
[patent_doc_number] => 05830791
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-11-03
[patent_title] => 'Manufacturing process for a DRAM with a buried region'
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[pdf_file] => patents/05/830/05830791.pdf
[firstpage_image] =>[orig_patent_app_number] => 871779
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/871779 | Manufacturing process for a DRAM with a buried region | Jun 8, 1997 | Issued |