| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 3860862
[patent_doc_number] => 05795811
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-08-18
[patent_title] => 'Method for forming insulating films in semiconductor devices'
[patent_app_type] => 1
[patent_app_number] => 8/578921
[patent_app_country] => US
[patent_app_date] => 1995-12-27
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[pdf_file] => patents/05/795/05795811.pdf
[firstpage_image] =>[orig_patent_app_number] => 578921
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/578921 | Method for forming insulating films in semiconductor devices | Dec 26, 1995 | Issued |
| 08/579436 | METHODS FOR FILLING TRENCHES IN A SEMICONDUCTOR WAFER | Dec 26, 1995 | Abandoned |
| 08/578930 | MODIFIED CLEAN RECIPE TO SUPPRESS FORMATION OF BPSG BUBBLE | Dec 26, 1995 | Abandoned |
Array
(
[id] => 3633392
[patent_doc_number] => 05631174
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-05-20
[patent_title] => 'Method for forming a spacer with a prograde profile'
[patent_app_type] => 1
[patent_app_number] => 8/576785
[patent_app_country] => US
[patent_app_date] => 1995-12-21
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[pdf_file] => patents/05/631/05631174.pdf
[firstpage_image] =>[orig_patent_app_number] => 576785
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/576785 | Method for forming a spacer with a prograde profile | Dec 20, 1995 | Issued |
Array
(
[id] => 3647301
[patent_doc_number] => 05683940
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-11-04
[patent_title] => 'Method of depositing a reflow SiO.sub.2 film'
[patent_app_type] => 1
[patent_app_number] => 8/575851
[patent_app_country] => US
[patent_app_date] => 1995-12-20
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[pdf_file] => patents/05/683/05683940.pdf
[firstpage_image] =>[orig_patent_app_number] => 575851
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/575851 | Method of depositing a reflow SiO.sub.2 film | Dec 19, 1995 | Issued |
Array
(
[id] => 4038611
[patent_doc_number] => 05926689
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-07-20
[patent_title] => 'Process for reducing circuit damage during PECVD in single wafer PECVD system'
[patent_app_type] => 1
[patent_app_number] => 8/574748
[patent_app_country] => US
[patent_app_date] => 1995-12-19
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 574748
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/574748 | Process for reducing circuit damage during PECVD in single wafer PECVD system | Dec 18, 1995 | Issued |
Array
(
[id] => 3601383
[patent_doc_number] => 05578505
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-11-26
[patent_title] => 'Methods for measuring the surface area of a semiconductor wafer'
[patent_app_type] => 1
[patent_app_number] => 8/573331
[patent_app_country] => US
[patent_app_date] => 1995-12-15
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 573331
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/573331 | Methods for measuring the surface area of a semiconductor wafer | Dec 14, 1995 | Issued |
Array
(
[id] => 4039358
[patent_doc_number] => 05926739
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-07-20
[patent_title] => 'Semiconductor processing method of promoting photoresist adhesion to an outer substrate layer predominately comprising silicon nitride'
[patent_app_type] => 1
[patent_app_number] => 8/567090
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 567090
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/567090 | Semiconductor processing method of promoting photoresist adhesion to an outer substrate layer predominately comprising silicon nitride | Dec 3, 1995 | Issued |
Array
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[id] => 3773676
[patent_doc_number] => 05817534
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-10-06
[patent_title] => 'RF plasma reactor with cleaning electrode for cleaning during processing of semiconductor wafers'
[patent_app_type] => 1
[patent_app_number] => 8/567376
[patent_app_country] => US
[patent_app_date] => 1995-12-04
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/817/05817534.pdf
[firstpage_image] =>[orig_patent_app_number] => 567376
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/567376 | RF plasma reactor with cleaning electrode for cleaning during processing of semiconductor wafers | Dec 3, 1995 | Issued |
Array
(
[id] => 3624824
[patent_doc_number] => 05620909
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-04-15
[patent_title] => 'Method of depositing thin passivating film on microminiature semiconductor devices'
[patent_app_type] => 1
[patent_app_number] => 8/566766
[patent_app_country] => US
[patent_app_date] => 1995-12-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 3281
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/620/05620909.pdf
[firstpage_image] =>[orig_patent_app_number] => 566766
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/566766 | Method of depositing thin passivating film on microminiature semiconductor devices | Dec 3, 1995 | Issued |
| 08/562205 | TRENCH SURROUNDED METAL PATTERN | Nov 21, 1995 | Abandoned |
Array
(
[id] => 4125380
[patent_doc_number] => 06127261
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-03
[patent_title] => 'Method of fabricating an integrated circuit including a tri-layer pre-metal interlayer dielectric compatible with advanced CMOS technologies'
[patent_app_type] => 1
[patent_app_number] => 8/559054
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[pdf_file] => patents/06/127/06127261.pdf
[firstpage_image] =>[orig_patent_app_number] => 559054
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/559054 | Method of fabricating an integrated circuit including a tri-layer pre-metal interlayer dielectric compatible with advanced CMOS technologies | Nov 15, 1995 | Issued |
Array
(
[id] => 4003171
[patent_doc_number] => 06004875
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-12-21
[patent_title] => 'Etch stop for use in etching of silicon oxide'
[patent_app_type] => 1
[patent_app_number] => 8/558777
[patent_app_country] => US
[patent_app_date] => 1995-11-15
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[firstpage_image] =>[orig_patent_app_number] => 558777
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/558777 | Etch stop for use in etching of silicon oxide | Nov 14, 1995 | Issued |
Array
(
[id] => 3838953
[patent_doc_number] => 05744399
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-04-28
[patent_title] => 'Process for forming low dielectric constant layers using fullerenes'
[patent_app_type] => 1
[patent_app_number] => 8/557721
[patent_app_country] => US
[patent_app_date] => 1995-11-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[pdf_file] => patents/05/744/05744399.pdf
[firstpage_image] =>[orig_patent_app_number] => 557721
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/557721 | Process for forming low dielectric constant layers using fullerenes | Nov 12, 1995 | Issued |
| 08/555908 | ELECTRON EMITTERS AND METHOD FOR FORMING THEM | Nov 12, 1995 | Abandoned |
| 08/548391 | METHOD AND APPARATUS FOR IMPROVING FILM STABILITY OF HALOGEN-DOPED SILICON OXIDE FILMS | Oct 25, 1995 | Abandoned |
Array
(
[id] => 3877115
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[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-03-17
[patent_title] => 'Spin-on conductor process for integrated circuits'
[patent_app_type] => 1
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[patent_app_country] => US
[patent_app_date] => 1995-10-23
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[firstpage_image] =>[orig_patent_app_number] => 553788
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/553788 | Spin-on conductor process for integrated circuits | Oct 22, 1995 | Issued |
Array
(
[id] => 3665769
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[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-02-04
[patent_title] => 'Manufacture of micro electron emitter'
[patent_app_type] => 1
[patent_app_number] => 8/544922
[patent_app_country] => US
[patent_app_date] => 1995-10-18
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[firstpage_image] =>[orig_patent_app_number] => 544922
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/544922 | Manufacture of micro electron emitter | Oct 17, 1995 | Issued |
Array
(
[id] => 3757079
[patent_doc_number] => 05721156
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-02-24
[patent_title] => 'Method of manufacturing a semiconductor device with a planarized integrated circuit'
[patent_app_type] => 1
[patent_app_number] => 8/538324
[patent_app_country] => US
[patent_app_date] => 1995-10-03
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[firstpage_image] =>[orig_patent_app_number] => 538324
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/538324 | Method of manufacturing a semiconductor device with a planarized integrated circuit | Oct 2, 1995 | Issued |
Array
(
[id] => 3647335
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[patent_kind] => NA
[patent_issue_date] => 1997-05-13
[patent_title] => 'Method for forming fluorine-doped glass having low concentrations of free fluorine'
[patent_app_type] => 1
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[patent_app_country] => US
[patent_app_date] => 1995-09-27
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/534721 | Method for forming fluorine-doped glass having low concentrations of free fluorine | Sep 26, 1995 | Issued |