Search

Kevin A. Kriess

Examiner (ID: 2741)

Most Active Art Unit
2316
Art Unit(s)
2307, 2755, 2316, 2787
Total Applications
665
Issued Applications
518
Pending Applications
18
Abandoned Applications
129

Applications

Application numberTitle of the applicationFiling DateStatus
07/117846 SINGLE-CHIP MICROCOMPUTER HAVING SECURITY MEMORY Nov 8, 1987 Abandoned
Array ( [id] => 2531021 [patent_doc_number] => 04878174 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-10-31 [patent_title] => 'Flexible ASIC microcomputer permitting the modular modification of dedicated functions and macroinstructions' [patent_app_type] => 1 [patent_app_number] => 7/116411 [patent_app_country] => US [patent_app_date] => 1987-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4462 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/878/04878174.pdf [firstpage_image] =>[orig_patent_app_number] => 116411 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/116411
Flexible ASIC microcomputer permitting the modular modification of dedicated functions and macroinstructions Nov 2, 1987 Issued
Array ( [id] => 2430837 [patent_doc_number] => 04780843 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-10-25 [patent_title] => 'Wait mode power reduction system and method for data processor' [patent_app_type] => 1 [patent_app_number] => 7/107899 [patent_app_country] => US [patent_app_date] => 1987-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2424 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/780/04780843.pdf [firstpage_image] =>[orig_patent_app_number] => 107899 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/107899
Wait mode power reduction system and method for data processor Oct 12, 1987 Issued
Array ( [id] => 2564214 [patent_doc_number] => 04814982 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-03-21 [patent_title] => 'Reconfigurable, multiprocessor system with protected, multiple, memories' [patent_app_type] => 1 [patent_app_number] => 7/107651 [patent_app_country] => US [patent_app_date] => 1987-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3472 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 307 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/814/04814982.pdf [firstpage_image] =>[orig_patent_app_number] => 107651 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/107651
Reconfigurable, multiprocessor system with protected, multiple, memories Oct 8, 1987 Issued
Array ( [id] => 2397629 [patent_doc_number] => 04754400 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-06-28 [patent_title] => 'Protocol validation system' [patent_app_type] => 1 [patent_app_number] => 7/106030 [patent_app_country] => US [patent_app_date] => 1987-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 30 [patent_no_of_words] => 11063 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 338 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/754/04754400.pdf [firstpage_image] =>[orig_patent_app_number] => 106030 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/106030
Protocol validation system Oct 7, 1987 Issued
Array ( [id] => 2528298 [patent_doc_number] => 04855948 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-08-08 [patent_title] => 'Bypass booster mechanisms for the line scanners of a communication controller' [patent_app_type] => 1 [patent_app_number] => 7/107432 [patent_app_country] => US [patent_app_date] => 1987-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 7099 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/855/04855948.pdf [firstpage_image] =>[orig_patent_app_number] => 107432 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/107432
Bypass booster mechanisms for the line scanners of a communication controller Oct 7, 1987 Issued
Array ( [id] => 2815623 [patent_doc_number] => 05115497 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-05-19 [patent_title] => 'Optically intraconnected computer employing dynamically reconfigurable holographic optical element' [patent_app_type] => 1 [patent_app_number] => 7/103192 [patent_app_country] => US [patent_app_date] => 1987-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 14 [patent_no_of_words] => 2145 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/115/05115497.pdf [firstpage_image] =>[orig_patent_app_number] => 103192 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/103192
Optically intraconnected computer employing dynamically reconfigurable holographic optical element Sep 30, 1987 Issued
Array ( [id] => 2609066 [patent_doc_number] => 04965882 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-10-23 [patent_title] => 'Method for operating a parallel processing system and related apparatus' [patent_app_type] => 1 [patent_app_number] => 7/103364 [patent_app_country] => US [patent_app_date] => 1987-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 6849 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 344 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/965/04965882.pdf [firstpage_image] =>[orig_patent_app_number] => 103364 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/103364
Method for operating a parallel processing system and related apparatus Sep 30, 1987 Issued
07/100533 APPARATUS AND METHOD FOR DISTRIBUTED DYNAMIC PRIORITY ARBITRATION FOR ACCESS TO A SHARED RESOURCE Sep 23, 1987 Abandoned
07/093188 METHOD AND APPARATUS FOR SUSPENDING AND RESTARTING A BUS CYCLE Sep 3, 1987 Abandoned
Array ( [id] => 2664828 [patent_doc_number] => 04930072 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-05-29 [patent_title] => 'Method for computing transitive closure' [patent_app_type] => 1 [patent_app_number] => 7/091236 [patent_app_country] => US [patent_app_date] => 1987-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 7717 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/930/04930072.pdf [firstpage_image] =>[orig_patent_app_number] => 091236 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/091236
Method for computing transitive closure Aug 30, 1987 Issued
Array ( [id] => 2490173 [patent_doc_number] => 04823257 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-04-18 [patent_title] => 'Information processing system having smart memories' [patent_app_type] => 1 [patent_app_number] => 7/083288 [patent_app_country] => US [patent_app_date] => 1987-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3272 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/823/04823257.pdf [firstpage_image] =>[orig_patent_app_number] => 083288 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/083288
Information processing system having smart memories Aug 9, 1987 Issued
07/081908 PARALLEL TRANSFER UTILITY FOR DATA TRANSFER BETWEEN A HOST COMPUTER AND A MICROPROCESSOR BASED SYSTEM Aug 4, 1987 Abandoned
Array ( [id] => 2676714 [patent_doc_number] => 05070473 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-12-03 [patent_title] => 'Microprocessor' [patent_app_type] => 1 [patent_app_number] => 7/077442 [patent_app_country] => US [patent_app_date] => 1987-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3051 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/070/05070473.pdf [firstpage_image] =>[orig_patent_app_number] => 077442 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/077442
Microprocessor Jul 23, 1987 Issued
07/055443 DISK DRIVE CONTROLLER May 27, 1987 Abandoned
07/044479 BACKPLANE BUS SYSTEM INCLUDING A PLURALITY OF NODES Apr 30, 1987 Abandoned
07/041047 INSTRUCTION STORAGE AND CACHE MISS RECOVERY IN A HIGH SPEED MULTIPROCESSING PARALLEL PROCESSING APPARATUS Apr 19, 1987 Abandoned
07/040705 RETRIEVAL OF RELATED RECORDS FROM A RELATIONAL DATABASE Apr 16, 1987 Abandoned
07/040702 INTERACTIVE CONSTRUCTION OF MEANS FOR DATABASE MANAGEMENT Apr 16, 1987 Abandoned
07/040706 INTERACTIVE ERROR HANDLING MEANS IN DATABASE MANAGEMENT Apr 16, 1987 Abandoned
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