Search

Kevin A. Parendo

Examiner (ID: 2896, Phone: (571)270-5030 , Office: P/2819 )

Most Active Art Unit
2823
Art Unit(s)
2823, 4122, 2896, 2819
Total Applications
837
Issued Applications
560
Pending Applications
85
Abandoned Applications
221

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14476615 [patent_doc_number] => 20190189957 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-20 [patent_title] => ORGANIC LIGHT EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/224924 [patent_app_country] => US [patent_app_date] => 2018-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8454 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16224924 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/224924
Organic light emitting display device having a seal pattern corresponding to a concave part Dec 18, 2018 Issued
Array ( [id] => 14163979 [patent_doc_number] => 20190109092 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-11 [patent_title] => POSITIONING STRUCTURE HAVING POSITIONING UNIT [patent_app_type] => utility [patent_app_number] => 16/216621 [patent_app_country] => US [patent_app_date] => 2018-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5408 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16216621 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/216621
POSITIONING STRUCTURE HAVING POSITIONING UNIT Dec 10, 2018 Abandoned
Array ( [id] => 16684382 [patent_doc_number] => 10943873 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-09 [patent_title] => Semiconductor device structure comprising a plurality of metal oxide fibers and method for forming the same [patent_app_type] => utility [patent_app_number] => 16/213788 [patent_app_country] => US [patent_app_date] => 2018-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 30 [patent_no_of_words] => 9169 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16213788 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/213788
Semiconductor device structure comprising a plurality of metal oxide fibers and method for forming the same Dec 6, 2018 Issued
Array ( [id] => 15984765 [patent_doc_number] => 10672721 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-02 [patent_title] => Method for fabricating an electronic device and a stacked electronic device [patent_app_type] => utility [patent_app_number] => 16/208038 [patent_app_country] => US [patent_app_date] => 2018-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 3225 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16208038 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/208038
Method for fabricating an electronic device and a stacked electronic device Dec 2, 2018 Issued
Array ( [id] => 17772610 [patent_doc_number] => 11404564 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-02 [patent_title] => Integrated circuit having a transistor, a diode, and a temperature sensor [patent_app_type] => utility [patent_app_number] => 16/208377 [patent_app_country] => US [patent_app_date] => 2018-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7966 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16208377 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/208377
Integrated circuit having a transistor, a diode, and a temperature sensor Dec 2, 2018 Issued
Array ( [id] => 17048117 [patent_doc_number] => 11101307 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-24 [patent_title] => Image sensor having stacked conformal films [patent_app_type] => utility [patent_app_number] => 16/202777 [patent_app_country] => US [patent_app_date] => 2018-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5232 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16202777 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/202777
Image sensor having stacked conformal films Nov 27, 2018 Issued
Array ( [id] => 15906471 [patent_doc_number] => 20200152756 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-14 [patent_title] => SOURCE AND DRAIN CONTACT CUT LAST PROCESS TO ENABLE WRAP-AROUND-CONTACT [patent_app_type] => utility [patent_app_number] => 16/188612 [patent_app_country] => US [patent_app_date] => 2018-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5833 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16188612 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/188612
Source and drain contact cut last process to enable wrap-around-contact Nov 12, 2018 Issued
Array ( [id] => 16565448 [patent_doc_number] => 10890814 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-12 [patent_title] => Display having dummy sub-pixels with dummy color resists [patent_app_type] => utility [patent_app_number] => 16/188623 [patent_app_country] => US [patent_app_date] => 2018-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8494 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16188623 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/188623
Display having dummy sub-pixels with dummy color resists Nov 12, 2018 Issued
Array ( [id] => 15703343 [patent_doc_number] => 10607858 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-31 [patent_title] => Semiconductor method for forming semiconductor structure having bump on tilting upper corner surface [patent_app_type] => utility [patent_app_number] => 16/183701 [patent_app_country] => US [patent_app_date] => 2018-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 3554 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16183701 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/183701
Semiconductor method for forming semiconductor structure having bump on tilting upper corner surface Nov 6, 2018 Issued
Array ( [id] => 16332480 [patent_doc_number] => 20200303446 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-24 [patent_title] => IMAGING ELEMENT, STACKED-TYPE IMAGING ELEMENT, AND SOLID-STATE IMAGING APPARATUS [patent_app_type] => utility [patent_app_number] => 16/768207 [patent_app_country] => US [patent_app_date] => 2018-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 45997 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16768207 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/768207
Imaging element, stacked-type imaging element, and solid-state imaging apparatus to improve charge transfer Oct 30, 2018 Issued
Array ( [id] => 13909649 [patent_doc_number] => 20190044029 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-07 [patent_title] => MUTILAYER STRUCTURE CONTAINING A CRYSTAL MATCHING LAYER FOR INCREASED SEMICONDUCTOR DEVICE PERFORMANCE [patent_app_type] => utility [patent_app_number] => 16/155825 [patent_app_country] => US [patent_app_date] => 2018-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5259 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16155825 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/155825
MUTILAYER STRUCTURE CONTAINING A CRYSTAL MATCHING LAYER FOR INCREASED SEMICONDUCTOR DEVICE PERFORMANCE Oct 8, 2018 Abandoned
Array ( [id] => 16911371 [patent_doc_number] => 11043420 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-22 [patent_title] => Fan-out wafer level packaging of semiconductor devices [patent_app_type] => utility [patent_app_number] => 16/145783 [patent_app_country] => US [patent_app_date] => 2018-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 5839 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16145783 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/145783
Fan-out wafer level packaging of semiconductor devices Sep 27, 2018 Issued
Array ( [id] => 15717803 [patent_doc_number] => 20200105669 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-02 [patent_title] => DESIGN AND PROCESS FOR A PRECISION RESISTOR [patent_app_type] => utility [patent_app_number] => 16/147112 [patent_app_country] => US [patent_app_date] => 2018-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5777 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16147112 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/147112
And process for a precision resistor Sep 27, 2018 Issued
Array ( [id] => 15688003 [patent_doc_number] => 20200098665 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-26 [patent_title] => NON-PLANAR CONFORMING HEATSINK [patent_app_type] => utility [patent_app_number] => 16/143373 [patent_app_country] => US [patent_app_date] => 2018-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7072 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16143373 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/143373
Non-planar conforming heatsink Sep 25, 2018 Issued
Array ( [id] => 18623995 [patent_doc_number] => 11757053 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-12 [patent_title] => Package substrate having a sacrificial region for heat sink attachment [patent_app_type] => utility [patent_app_number] => 16/651425 [patent_app_country] => US [patent_app_date] => 2018-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 33 [patent_no_of_words] => 18016 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16651425 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/651425
Package substrate having a sacrificial region for heat sink attachment Sep 20, 2018 Issued
Array ( [id] => 13582203 [patent_doc_number] => 20180342650 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-29 [patent_title] => LIGHT EMITTING DIODE STRUCTURE [patent_app_type] => utility [patent_app_number] => 16/051884 [patent_app_country] => US [patent_app_date] => 2018-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4307 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16051884 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/051884
Light emitting diode having patterned mirror layer Jul 31, 2018 Issued
Array ( [id] => 14079801 [patent_doc_number] => 20190088788 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-21 [patent_title] => Thin Film Transistor and Method of Fabricating the Same, Array Substrate and Display Device [patent_app_type] => utility [patent_app_number] => 16/050294 [patent_app_country] => US [patent_app_date] => 2018-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6776 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16050294 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/050294
Thin film transistor and method of fabricating the same, array substrate and display device Jul 30, 2018 Issued
Array ( [id] => 14985187 [patent_doc_number] => 10446514 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-15 [patent_title] => Combing bump structure and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 16/048357 [patent_app_country] => US [patent_app_date] => 2018-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 2730 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16048357 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/048357
Combing bump structure and manufacturing method thereof Jul 29, 2018 Issued
Array ( [id] => 13785669 [patent_doc_number] => 20190006373 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-03 [patent_title] => PREVENTING GATE-TO-CONTACT BRIDGING BY REDUCING CONTACT DIMENSIONS IN FINFET SRAM [patent_app_type] => utility [patent_app_number] => 16/046188 [patent_app_country] => US [patent_app_date] => 2018-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7002 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16046188 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/046188
Preventing gate-to-contact bridging by reducing contact dimensions in FinFET SRAM Jul 25, 2018 Issued
Array ( [id] => 13419837 [patent_doc_number] => 20180261461 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-13 [patent_title] => SALICIDE FORMATION USING A CAP LAYER [patent_app_type] => utility [patent_app_number] => 15/981665 [patent_app_country] => US [patent_app_date] => 2018-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3084 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15981665 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/981665
SALICIDE FORMATION USING A CAP LAYER May 15, 2018 Abandoned
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