Search

Kevin A. Parendo

Examiner (ID: 2896, Phone: (571)270-5030 , Office: P/2819 )

Most Active Art Unit
2823
Art Unit(s)
2823, 4122, 2896, 2819
Total Applications
837
Issued Applications
560
Pending Applications
85
Abandoned Applications
221

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15093075 [patent_doc_number] => 20190341349 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-07 [patent_title] => SIDE MOUNTED INTERCONNECT BRIDGES [patent_app_type] => utility [patent_app_number] => 16/474005 [patent_app_country] => US [patent_app_date] => 2017-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7206 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16474005 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/474005
Side mounted interconnect bridges Mar 28, 2017 Issued
Array ( [id] => 11732857 [patent_doc_number] => 20170194301 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-06 [patent_title] => 'Power Device Cassette With Auxiliary Emitter Contact' [patent_app_type] => utility [patent_app_number] => 15/465561 [patent_app_country] => US [patent_app_date] => 2017-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 9139 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15465561 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/465561
Power device cassette with auxiliary emitter contact Mar 20, 2017 Issued
Array ( [id] => 16951724 [patent_doc_number] => 20210210416 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-08 [patent_title] => METHOD FOR PRODUCING A SUBSTRATE PLATE, SUBSTRATE PLATE, METHOD FOR PRODUCING A SEMICONDUCTOR MODULE AND SEMICONDUCTOR MODULE [patent_app_type] => utility [patent_app_number] => 15/999689 [patent_app_country] => US [patent_app_date] => 2017-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5966 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15999689 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/999689
METHOD FOR PRODUCING A SUBSTRATE PLATE, SUBSTRATE PLATE, METHOD FOR PRODUCING A SEMICONDUCTOR MODULE AND SEMICONDUCTOR MODULE Feb 8, 2017 Abandoned
Array ( [id] => 13769497 [patent_doc_number] => 10177098 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-08 [patent_title] => Method for fabricating an electronic device and a stacked electronic device [patent_app_type] => utility [patent_app_number] => 15/410230 [patent_app_country] => US [patent_app_date] => 2017-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 3206 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15410230 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/410230
Method for fabricating an electronic device and a stacked electronic device Jan 18, 2017 Issued
Array ( [id] => 16464290 [patent_doc_number] => 10847653 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-24 [patent_title] => Semiconductor device having metallic source and drain regions [patent_app_type] => utility [patent_app_number] => 15/408294 [patent_app_country] => US [patent_app_date] => 2017-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 7487 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15408294 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/408294
Semiconductor device having metallic source and drain regions Jan 16, 2017 Issued
Array ( [id] => 17332379 [patent_doc_number] => 11222847 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-11 [patent_title] => Enabling long interconnect bridges [patent_app_type] => utility [patent_app_number] => 16/469084 [patent_app_country] => US [patent_app_date] => 2016-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4820 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16469084 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/469084
Enabling long interconnect bridges Dec 27, 2016 Issued
Array ( [id] => 11557860 [patent_doc_number] => 20170104106 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-13 [patent_title] => 'DECOUPLING FINFET CAPACITORS' [patent_app_type] => utility [patent_app_number] => 15/389173 [patent_app_country] => US [patent_app_date] => 2016-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5116 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15389173 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/389173
Decoupling finFET capacitors Dec 21, 2016 Issued
Array ( [id] => 11630809 [patent_doc_number] => 20170140998 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-18 [patent_title] => 'SEMICONDUCTOR DEVICE INCLUDING SHALLOW TRENCH ISOLATION STRUCTURES' [patent_app_type] => utility [patent_app_number] => 15/384109 [patent_app_country] => US [patent_app_date] => 2016-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7042 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15384109 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/384109
SEMICONDUCTOR DEVICE INCLUDING SHALLOW TRENCH ISOLATION STRUCTURES Dec 18, 2016 Abandoned
Array ( [id] => 16356646 [patent_doc_number] => 10797164 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-06 [patent_title] => FinFETs having epitaxial capping layer on fin and methods for forming the same [patent_app_type] => utility [patent_app_number] => 15/367871 [patent_app_country] => US [patent_app_date] => 2016-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4415 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15367871 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/367871
FinFETs having epitaxial capping layer on fin and methods for forming the same Dec 1, 2016 Issued
Array ( [id] => 17700403 [patent_doc_number] => 11374138 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-28 [patent_title] => Imaging element, solid state imaging device, and electronic device having an amorphous oxide electrode comprising tungsten [patent_app_type] => utility [patent_app_number] => 16/061456 [patent_app_country] => US [patent_app_date] => 2016-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 12799 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16061456 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/061456
Imaging element, solid state imaging device, and electronic device having an amorphous oxide electrode comprising tungsten Nov 29, 2016 Issued
Array ( [id] => 15200591 [patent_doc_number] => 10497799 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-03 [patent_title] => Dummy dielectric fins for finFETs with silicon and silicon germanium channels [patent_app_type] => utility [patent_app_number] => 15/353314 [patent_app_country] => US [patent_app_date] => 2016-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 5177 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15353314 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/353314
Dummy dielectric fins for finFETs with silicon and silicon germanium channels Nov 15, 2016 Issued
Array ( [id] => 11475903 [patent_doc_number] => 20170062686 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-02 [patent_title] => 'METHOD OF MAKING LAYERED STRUCTURE WITH METAL LAYERS' [patent_app_type] => utility [patent_app_number] => 15/350979 [patent_app_country] => US [patent_app_date] => 2016-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 28915 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15350979 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/350979
Method of making layered structure with metal layers using resist patterns and electrolytic plating Nov 13, 2016 Issued
Array ( [id] => 11439360 [patent_doc_number] => 20170040382 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-09 [patent_title] => 'SEMICONDUCTOR APPARATUS WITH VARIABLE RESISTOR HAVING TAPERED DOUBLE-LAYERED SIDEWALL SPACERS' [patent_app_type] => utility [patent_app_number] => 15/298050 [patent_app_country] => US [patent_app_date] => 2016-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2955 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15298050 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/298050
SEMICONDUCTOR APPARATUS WITH VARIABLE RESISTOR HAVING TAPERED DOUBLE-LAYERED SIDEWALL SPACERS Oct 18, 2016 Abandoned
Array ( [id] => 11883723 [patent_doc_number] => 09754905 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-09-05 [patent_title] => 'Final passivation for wafer level warpage and ULK stress reduction' [patent_app_type] => utility [patent_app_number] => 15/292433 [patent_app_country] => US [patent_app_date] => 2016-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6285 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15292433 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/292433
Final passivation for wafer level warpage and ULK stress reduction Oct 12, 2016 Issued
Array ( [id] => 16820171 [patent_doc_number] => 11005012 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-11 [patent_title] => Wavelength converted light emitting device with textured substrate [patent_app_type] => utility [patent_app_number] => 15/769134 [patent_app_country] => US [patent_app_date] => 2016-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 4300 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15769134 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/769134
Wavelength converted light emitting device with textured substrate Oct 9, 2016 Issued
Array ( [id] => 13071181 [patent_doc_number] => 10056376 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-21 [patent_title] => Ferroelectric FinFET [patent_app_type] => utility [patent_app_number] => 15/238023 [patent_app_country] => US [patent_app_date] => 2016-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 6197 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15238023 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/238023
Ferroelectric FinFET Aug 15, 2016 Issued
Array ( [id] => 11608101 [patent_doc_number] => 20170125406 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-04 [patent_title] => 'Methods of Manufacturing Transistors Including Forming a Depression in a Surface of a Covering of Resist Material' [patent_app_type] => utility [patent_app_number] => 15/236057 [patent_app_country] => US [patent_app_date] => 2016-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 41 [patent_no_of_words] => 13895 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15236057 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/236057
Methods of manufacturing transistors including forming a depression in a surface of a covering of resist material Aug 11, 2016 Issued
Array ( [id] => 13667927 [patent_doc_number] => 10164146 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-25 [patent_title] => P-side layers for short wavelength light emitters [patent_app_type] => utility [patent_app_number] => 15/209715 [patent_app_country] => US [patent_app_date] => 2016-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 26 [patent_no_of_words] => 8933 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15209715 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/209715
P-side layers for short wavelength light emitters Jul 12, 2016 Issued
Array ( [id] => 15200583 [patent_doc_number] => 10497795 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-03 [patent_title] => Triple well isolated diode and method of making [patent_app_type] => utility [patent_app_number] => 15/200727 [patent_app_country] => US [patent_app_date] => 2016-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4710 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15200727 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/200727
Triple well isolated diode and method of making Jun 30, 2016 Issued
Array ( [id] => 13682835 [patent_doc_number] => 20160380154 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-29 [patent_title] => MULTILAYER STRUCTURE CONTAINING A CRYSTAL MATCHING LAYER FOR INCREASED SEMICONDUCTOR DEVICE PERFORMANCE [patent_app_type] => utility [patent_app_number] => 15/194517 [patent_app_country] => US [patent_app_date] => 2016-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5230 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15194517 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/194517
MULTILAYER STRUCTURE CONTAINING A CRYSTAL MATCHING LAYER FOR INCREASED SEMICONDUCTOR DEVICE PERFORMANCE Jun 26, 2016 Abandoned
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