Search

Kevin A. Parendo

Examiner (ID: 2896, Phone: (571)270-5030 , Office: P/2819 )

Most Active Art Unit
2823
Art Unit(s)
2823, 4122, 2896, 2819
Total Applications
837
Issued Applications
560
Pending Applications
85
Abandoned Applications
221

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9668054 [patent_doc_number] => 20140231917 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-21 [patent_title] => 'FINFET AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/223950 [patent_app_country] => US [patent_app_date] => 2014-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 4414 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14223950 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/223950
FinFET having gate in place of sacrificial spacer source/drain mask Mar 23, 2014 Issued
Array ( [id] => 10858222 [patent_doc_number] => 08884426 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-11 [patent_title] => 'Semiconductor device including cooler' [patent_app_type] => utility [patent_app_number] => 14/220277 [patent_app_country] => US [patent_app_date] => 2014-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 25 [patent_no_of_words] => 10183 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14220277 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/220277
Semiconductor device including cooler Mar 19, 2014 Issued
Array ( [id] => 9754018 [patent_doc_number] => 20140284718 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-25 [patent_title] => 'METHOD OF REDUCION GRAPHENE OXIDE AND REDUCED GRAPHENE OXIDE OBTAINED BY THE METHOD, AND THIN FILM TRANSISTOR INCLUDING THE REDUCED GRAPHENE OXIDE' [patent_app_type] => utility [patent_app_number] => 14/196058 [patent_app_country] => US [patent_app_date] => 2014-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3694 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14196058 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/196058
METHOD OF REDUCION GRAPHENE OXIDE AND REDUCED GRAPHENE OXIDE OBTAINED BY THE METHOD, AND THIN FILM TRANSISTOR INCLUDING THE REDUCED GRAPHENE OXIDE Mar 3, 2014 Abandoned
Array ( [id] => 10493187 [patent_doc_number] => 20150378209 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-31 [patent_title] => 'SUBSTRATE FOR ELECTRO-OPTICAL DEVICE, ELECTRO-OPTICAL DEVICE, ELECTRONIC EQUIPMENT, AND METHOD FOR MANUFACTURING SUBSTRATE FOR ELECTRO-OPTICAL DEVICE' [patent_app_type] => utility [patent_app_number] => 14/766796 [patent_app_country] => US [patent_app_date] => 2014-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 15249 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14766796 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/766796
SUBSTRATE FOR ELECTRO-OPTICAL DEVICE, ELECTRO-OPTICAL DEVICE, ELECTRONIC EQUIPMENT, AND METHOD FOR MANUFACTURING SUBSTRATE FOR ELECTRO-OPTICAL DEVICE Mar 2, 2014 Abandoned
Array ( [id] => 10118801 [patent_doc_number] => 09153692 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-06 [patent_title] => 'Semiconductor device having a stress film on a side surface of a fin' [patent_app_type] => utility [patent_app_number] => 14/194837 [patent_app_country] => US [patent_app_date] => 2014-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 30 [patent_no_of_words] => 8556 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14194837 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/194837
Semiconductor device having a stress film on a side surface of a fin Mar 2, 2014 Issued
Array ( [id] => 9697038 [patent_doc_number] => 20140246723 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-04 [patent_title] => 'METHOD FOR MANUFACTURING A FIN MOS TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 14/193833 [patent_app_country] => US [patent_app_date] => 2014-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4672 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14193833 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/193833
Method for manufacturing a fin MOS transistor Feb 27, 2014 Issued
Array ( [id] => 9728919 [patent_doc_number] => 20140264626 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'METHOD FOR FORMING A GATE ELECTRODE OF A SEMICONDUCTOR DEVICE, GATE ELECTRODE STRUCTURE FOR A SEMICONDUCTOR DEVICE AND ACCORDING SEMICONDUCTOR DEVICE STRUCTURE' [patent_app_type] => utility [patent_app_number] => 14/174474 [patent_app_country] => US [patent_app_date] => 2014-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8053 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14174474 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/174474
METHOD FOR FORMING A GATE ELECTRODE OF A SEMICONDUCTOR DEVICE, GATE ELECTRODE STRUCTURE FOR A SEMICONDUCTOR DEVICE AND ACCORDING SEMICONDUCTOR DEVICE STRUCTURE Feb 5, 2014 Abandoned
Array ( [id] => 10903294 [patent_doc_number] => 20140306307 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-16 [patent_title] => 'BACKSIDE NANOSCALE TEXTURING TO IMPROVE IR RESPONSE OF SILICON SOLAR CELLS AND PHOTODETECTORS' [patent_app_type] => utility [patent_app_number] => 14/174746 [patent_app_country] => US [patent_app_date] => 2014-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6130 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14174746 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/174746
BACKSIDE NANOSCALE TEXTURING TO IMPROVE IR RESPONSE OF SILICON SOLAR CELLS AND PHOTODETECTORS Feb 5, 2014 Abandoned
Array ( [id] => 9508762 [patent_doc_number] => 20140145253 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-29 [patent_title] => 'ASYMMETRIC DENSE FLOATING GATE NONVOLATILE MEMORY WITH DECOUPLED CAPACITOR' [patent_app_type] => utility [patent_app_number] => 14/167045 [patent_app_country] => US [patent_app_date] => 2014-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 11169 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14167045 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/167045
Asymmetric dense floating gate nonvolatile memory with decoupled capacitor Jan 28, 2014 Issued
Array ( [id] => 9898716 [patent_doc_number] => 20150053915 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-26 [patent_title] => 'Light Emitting Diode' [patent_app_type] => utility [patent_app_number] => 14/164247 [patent_app_country] => US [patent_app_date] => 2014-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2643 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14164247 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/164247
High illumination efficiency light emitting diode Jan 25, 2014 Issued
Array ( [id] => 10563724 [patent_doc_number] => 09287406 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-15 [patent_title] => 'Dual-mode transistor devices and methods for operating same' [patent_app_type] => utility [patent_app_number] => 14/163639 [patent_app_country] => US [patent_app_date] => 2014-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 34 [patent_no_of_words] => 9906 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14163639 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/163639
Dual-mode transistor devices and methods for operating same Jan 23, 2014 Issued
Array ( [id] => 10659796 [patent_doc_number] => 20160005940 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-07 [patent_title] => 'DEVICE HAVING AT LEAST ONE OPTOELECTRONIC SEMICONDUCTOR COMPONENT' [patent_app_type] => utility [patent_app_number] => 14/766420 [patent_app_country] => US [patent_app_date] => 2014-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5216 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14766420 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/766420
Optoelectronic semiconductor device having contact track with relieved thermo-mechanical stress Jan 22, 2014 Issued
Array ( [id] => 9668053 [patent_doc_number] => 20140231916 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-21 [patent_title] => 'Transistor with coupled gate and ground plane' [patent_app_type] => utility [patent_app_number] => 14/156559 [patent_app_country] => US [patent_app_date] => 2014-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5096 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14156559 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/156559
Transistor with coupled gate and ground plane Jan 15, 2014 Issued
Array ( [id] => 10455524 [patent_doc_number] => 20150340540 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-26 [patent_title] => 'METHODS OF IMPRINT PATTERNING OF IRREGULAR SURFACE' [patent_app_type] => utility [patent_app_number] => 14/156521 [patent_app_country] => US [patent_app_date] => 2014-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 12774 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14156521 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/156521
Methods of imprint patterning of irregular surface Jan 15, 2014 Issued
Array ( [id] => 9477362 [patent_doc_number] => 20140134825 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-15 [patent_title] => 'LOW CAPACITANCE TRANSIENT VOLTAGE SUPPRESSOR (TVS) WITH REDUCED CLAMPING VOLTAGE' [patent_app_type] => utility [patent_app_number] => 14/157416 [patent_app_country] => US [patent_app_date] => 2014-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6151 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14157416 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/157416
Low capacitance transient voltage suppressor (TVS) with reduced clamping voltage Jan 15, 2014 Issued
Array ( [id] => 10537712 [patent_doc_number] => 09263346 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-16 [patent_title] => 'Semiconductor device with silicon layer containing carbon' [patent_app_type] => utility [patent_app_number] => 14/155708 [patent_app_country] => US [patent_app_date] => 2014-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 33 [patent_no_of_words] => 12270 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14155708 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/155708
Semiconductor device with silicon layer containing carbon Jan 14, 2014 Issued
Array ( [id] => 11207795 [patent_doc_number] => 09437425 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-06 [patent_title] => 'Methods for integrating lead and graphene growth and devices formed therefrom' [patent_app_type] => utility [patent_app_number] => 14/760462 [patent_app_country] => US [patent_app_date] => 2014-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 23026 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14760462 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/760462
Methods for integrating lead and graphene growth and devices formed therefrom Jan 9, 2014 Issued
Array ( [id] => 9594652 [patent_doc_number] => 20140191329 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-10 [patent_title] => 'METHOD FOR PRODUCING METAL CONTACTS WITHIN AN INTEGRATED CIRCUIT, AND CORRESPONDING INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 14/143100 [patent_app_country] => US [patent_app_date] => 2013-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3600 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14143100 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/143100
METHOD FOR PRODUCING METAL CONTACTS WITHIN AN INTEGRATED CIRCUIT, AND CORRESPONDING INTEGRATED CIRCUIT Dec 29, 2013 Abandoned
Array ( [id] => 10903272 [patent_doc_number] => 20140306285 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-16 [patent_title] => 'SEMICONDUCTOR POWER DEVICE' [patent_app_type] => utility [patent_app_number] => 14/136739 [patent_app_country] => US [patent_app_date] => 2013-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 8328 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14136739 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/136739
Lateral double-diffused MOS transistor having deeper drain region than source region Dec 19, 2013 Issued
Array ( [id] => 9729040 [patent_doc_number] => 20140264747 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'Deposition of Anisotropic Dielectric Layers Orientationally Matched to the Physically Separated Substrate' [patent_app_type] => utility [patent_app_number] => 14/137003 [patent_app_country] => US [patent_app_date] => 2013-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7546 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14137003 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/137003
Deposition of anisotropic dielectric layers orientationally matched to the physically separated substrate Dec 19, 2013 Issued
Menu