Search

Kevin A. Parendo

Examiner (ID: 2896, Phone: (571)270-5030 , Office: P/2819 )

Most Active Art Unit
2823
Art Unit(s)
2823, 4122, 2896, 2819
Total Applications
837
Issued Applications
560
Pending Applications
85
Abandoned Applications
221

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8257562 [patent_doc_number] => 08207040 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-26 [patent_title] => 'Methods of manufacturing semiconductor devices including forming (111) facets in silicon capping layers on source/drain regions' [patent_app_type] => utility [patent_app_number] => 13/021029 [patent_app_country] => US [patent_app_date] => 2011-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 7859 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13021029 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/021029
Methods of manufacturing semiconductor devices including forming (111) facets in silicon capping layers on source/drain regions Feb 3, 2011 Issued
Array ( [id] => 6111756 [patent_doc_number] => 20110189846 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-04 [patent_title] => 'METHODS OF MANUFACTURING NON-VOLATILE MEMORY DEVICES' [patent_app_type] => utility [patent_app_number] => 13/020979 [patent_app_country] => US [patent_app_date] => 2011-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 12237 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0189/20110189846.pdf [firstpage_image] =>[orig_patent_app_number] => 13020979 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/020979
METHODS OF MANUFACTURING NON-VOLATILE MEMORY DEVICES Feb 3, 2011 Abandoned
Array ( [id] => 8630410 [patent_doc_number] => 08362482 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-29 [patent_title] => 'Semiconductor device and structure' [patent_app_type] => utility [patent_app_number] => 13/016313 [patent_app_country] => US [patent_app_date] => 2011-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 522 [patent_figures_cnt] => 668 [patent_no_of_words] => 118284 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13016313 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/016313
Semiconductor device and structure Jan 27, 2011 Issued
Array ( [id] => 6102258 [patent_doc_number] => 20110165751 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-07 [patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/981408 [patent_app_country] => US [patent_app_date] => 2010-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2759 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0165/20110165751.pdf [firstpage_image] =>[orig_patent_app_number] => 12981408 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/981408
Using a mesh to form a lower electrode in a capacitor Dec 28, 2010 Issued
Array ( [id] => 7510968 [patent_doc_number] => 20110256678 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-20 [patent_title] => 'METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/981204 [patent_app_country] => US [patent_app_date] => 2010-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3441 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0256/20110256678.pdf [firstpage_image] =>[orig_patent_app_number] => 12981204 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/981204
Method for manufacturing a capacitor of a semiconductor device Dec 28, 2010 Issued
Array ( [id] => 8189112 [patent_doc_number] => 08183146 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-22 [patent_title] => 'Manufacturing method for a buried circuit structure' [patent_app_type] => utility [patent_app_number] => 12/980349 [patent_app_country] => US [patent_app_date] => 2010-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 3626 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/183/08183146.pdf [firstpage_image] =>[orig_patent_app_number] => 12980349 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/980349
Manufacturing method for a buried circuit structure Dec 28, 2010 Issued
Array ( [id] => 8363561 [patent_doc_number] => 08252624 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-28 [patent_title] => 'Method of manufacturing thin film solar cells having a high conversion efficiency' [patent_app_type] => utility [patent_app_number] => 12/980132 [patent_app_country] => US [patent_app_date] => 2010-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 23489 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12980132 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/980132
Method of manufacturing thin film solar cells having a high conversion efficiency Dec 27, 2010 Issued
Array ( [id] => 6161902 [patent_doc_number] => 20110159659 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-30 [patent_title] => 'Novel Manufacturing Approach for Collector and N Type Buried Layer Of Bipolar Transistor' [patent_app_type] => utility [patent_app_number] => 12/979907 [patent_app_country] => US [patent_app_date] => 2010-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3279 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0159/20110159659.pdf [firstpage_image] =>[orig_patent_app_number] => 12979907 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/979907
Manufacturing approach for collector and a buried layer of bipolar transistor Dec 27, 2010 Issued
Array ( [id] => 8064719 [patent_doc_number] => 20110244663 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-06 [patent_title] => 'FORMING A COMPOUND-NITRIDE STRUCTURE THAT INCLUDES A NUCLEATION LAYER' [patent_app_type] => utility [patent_app_number] => 12/980060 [patent_app_country] => US [patent_app_date] => 2010-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8682 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0244/20110244663.pdf [firstpage_image] =>[orig_patent_app_number] => 12980060 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/980060
FORMING A COMPOUND-NITRIDE STRUCTURE THAT INCLUDES A NUCLEATION LAYER Dec 27, 2010 Abandoned
Array ( [id] => 8759975 [patent_doc_number] => 08420495 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-16 [patent_title] => 'Manufacturing approach for collector and a buried layer of bipolar transistor' [patent_app_type] => utility [patent_app_number] => 12/979999 [patent_app_country] => US [patent_app_date] => 2010-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2168 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12979999 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/979999
Manufacturing approach for collector and a buried layer of bipolar transistor Dec 27, 2010 Issued
Array ( [id] => 8265400 [patent_doc_number] => 20120164827 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-28 [patent_title] => 'FABRICATION OF THROUGH-SILICON VIAS ON SILICON WAFERS' [patent_app_type] => utility [patent_app_number] => 12/978129 [patent_app_country] => US [patent_app_date] => 2010-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 19098 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12978129 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/978129
Fabrication of through-silicon vias on silicon wafers Dec 22, 2010 Issued
Array ( [id] => 8265401 [patent_doc_number] => 20120164829 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-28 [patent_title] => 'FABRICATION OF THROUGH-SILICON VIAS ON SILICON WAFERS' [patent_app_type] => utility [patent_app_number] => 12/977060 [patent_app_country] => US [patent_app_date] => 2010-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 19056 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12977060 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/977060
Fabrication of through-silicon vias on silicon wafers Dec 21, 2010 Issued
Array ( [id] => 8213961 [patent_doc_number] => 08193015 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-05 [patent_title] => 'Method of forming a light-emitting-diode array with polymer between light emitting devices' [patent_app_type] => utility [patent_app_number] => 12/975068 [patent_app_country] => US [patent_app_date] => 2010-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 3110 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/193/08193015.pdf [firstpage_image] =>[orig_patent_app_number] => 12975068 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/975068
Method of forming a light-emitting-diode array with polymer between light emitting devices Dec 20, 2010 Issued
Array ( [id] => 6161836 [patent_doc_number] => 20110159642 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-30 [patent_title] => 'TAPE FOR HOLDING CHIP, METHOD OF HOLDING CHIP-SHAPED WORKPIECE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING TAPE FOR HOLDING CHIP, AND METHOD OF MANUFACTURING TAPE FOR HOLDING CHIP' [patent_app_type] => utility [patent_app_number] => 12/969959 [patent_app_country] => US [patent_app_date] => 2010-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 20884 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0159/20110159642.pdf [firstpage_image] =>[orig_patent_app_number] => 12969959 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/969959
Tape for holding chip, method of holding chip-shaped workpiece, method of manufacturing semiconductor device using tape for holding chip, and method of manufacturing tape for holding chip Dec 15, 2010 Issued
Array ( [id] => 7773936 [patent_doc_number] => 08119493 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-21 [patent_title] => 'Method of forming a semiconductor device an alignment mark formed in a groove' [patent_app_type] => utility [patent_app_number] => 12/970197 [patent_app_country] => US [patent_app_date] => 2010-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 64 [patent_no_of_words] => 14134 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/119/08119493.pdf [firstpage_image] =>[orig_patent_app_number] => 12970197 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/970197
Method of forming a semiconductor device an alignment mark formed in a groove Dec 15, 2010 Issued
Array ( [id] => 8305792 [patent_doc_number] => 08227326 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-24 [patent_title] => 'Laser crystallization of amorphous silicon layer' [patent_app_type] => utility [patent_app_number] => 12/970580 [patent_app_country] => US [patent_app_date] => 2010-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 4002 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12970580 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/970580
Laser crystallization of amorphous silicon layer Dec 15, 2010 Issued
Array ( [id] => 5971017 [patent_doc_number] => 20110151592 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-23 [patent_title] => 'METHODS FOR MONITORING THE AMOUNT OF CONTAMINATION IMPARTED INTO SEMICONDUCTOR WAFERS DURING WAFER PROCESSING' [patent_app_type] => utility [patent_app_number] => 12/970139 [patent_app_country] => US [patent_app_date] => 2010-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6969 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0151/20110151592.pdf [firstpage_image] =>[orig_patent_app_number] => 12970139 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/970139
Methods for monitoring the amount of contamination imparted into semiconductor wafers during wafer processing Dec 15, 2010 Issued
Array ( [id] => 5971096 [patent_doc_number] => 20110151611 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-23 [patent_title] => 'METHOD FOR MANUFACTURING SOLAR CELLS' [patent_app_type] => utility [patent_app_number] => 12/970932 [patent_app_country] => US [patent_app_date] => 2010-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2373 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0151/20110151611.pdf [firstpage_image] =>[orig_patent_app_number] => 12970932 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/970932
Forming protrusions in solar cells Dec 15, 2010 Issued
Array ( [id] => 8252536 [patent_doc_number] => 20120156854 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-21 [patent_title] => 'METHOD OF FORMING STACKED METAL OXIDE LAYERS' [patent_app_type] => utility [patent_app_number] => 12/970835 [patent_app_country] => US [patent_app_date] => 2010-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 13021 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0156/20120156854.pdf [firstpage_image] =>[orig_patent_app_number] => 12970835 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/970835
Method of forming stacked metal oxide layers Dec 15, 2010 Issued
Array ( [id] => 6038981 [patent_doc_number] => 20110092030 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-21 [patent_title] => 'SYSTEM COMPRISING A SEMICONDUCTOR DEVICE AND STRUCTURE' [patent_app_type] => utility [patent_app_number] => 12/970602 [patent_app_country] => US [patent_app_date] => 2010-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 516 [patent_figures_cnt] => 516 [patent_no_of_words] => 114910 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0092/20110092030.pdf [firstpage_image] =>[orig_patent_app_number] => 12970602 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/970602
Method of manufacturing a three dimensional integrated circuit by transfer of a mono-crystalline layer Dec 15, 2010 Issued
Menu