
Kevin H. Lee
Examiner (ID: 19464, Phone: (571)270-5651 , Office: P/2475 )
| Most Active Art Unit | 2475 |
| Art Unit(s) | 4125, 2478, 2475, 2419 |
| Total Applications | 317 |
| Issued Applications | 227 |
| Pending Applications | 1 |
| Abandoned Applications | 90 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 11510963
[patent_doc_number] => 09602136
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-03-21
[patent_title] => 'Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 4/15 and 256-symbol mapping, and bit interleaving method using same'
[patent_app_type] => utility
[patent_app_number] => 14/636053
[patent_app_country] => US
[patent_app_date] => 2015-03-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 6979
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 373
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14636053
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/636053 | Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 4/15 and 256-symbol mapping, and bit interleaving method using same | Mar 1, 2015 | Issued |
Array
(
[id] => 10363368
[patent_doc_number] => 20150248373
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-09-03
[patent_title] => 'BIT ALLOCATION OVER A SHARED BUS TO FACILITATE AN ERROR DETECTION OPTIMIZATION'
[patent_app_type] => utility
[patent_app_number] => 14/634106
[patent_app_country] => US
[patent_app_date] => 2015-02-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 37
[patent_figures_cnt] => 37
[patent_no_of_words] => 13574
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14634106
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/634106 | BIT ALLOCATION OVER A SHARED BUS TO FACILITATE AN ERROR DETECTION OPTIMIZATION | Feb 26, 2015 | Abandoned |
Array
(
[id] => 11510958
[patent_doc_number] => 09602131
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-03-21
[patent_title] => 'Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 3/15 and 16-symbol mapping, and bit interleaving method using same'
[patent_app_type] => utility
[patent_app_number] => 14/626238
[patent_app_country] => US
[patent_app_date] => 2015-02-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 6945
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 371
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14626238
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/626238 | Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 3/15 and 16-symbol mapping, and bit interleaving method using same | Feb 18, 2015 | Issued |
Array
(
[id] => 10708908
[patent_doc_number] => 20160055055
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-02-25
[patent_title] => 'MEMORY SYSTEM AND ERROR CORRECTION DECODING METHOD'
[patent_app_type] => utility
[patent_app_number] => 14/626072
[patent_app_country] => US
[patent_app_date] => 2015-02-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 9599
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14626072
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/626072 | MEMORY SYSTEM AND ERROR CORRECTION DECODING METHOD | Feb 18, 2015 | |
Array
(
[id] => 10401520
[patent_doc_number] => 20150286529
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-10-08
[patent_title] => 'MEMORY DEVICE HAVING CONTROLLER WITH LOCAL MEMORY'
[patent_app_type] => utility
[patent_app_number] => 14/620852
[patent_app_country] => US
[patent_app_date] => 2015-02-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3309
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14620852
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/620852 | MEMORY DEVICE HAVING CONTROLLER WITH LOCAL MEMORY | Feb 11, 2015 | Abandoned |
Array
(
[id] => 10275876
[patent_doc_number] => 20150160874
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-06-11
[patent_title] => 'INTEGRITY OF AN ADDRESS BUS'
[patent_app_type] => utility
[patent_app_number] => 14/620474
[patent_app_country] => US
[patent_app_date] => 2015-02-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3818
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14620474
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/620474 | Integrity of an address bus | Feb 11, 2015 | Issued |
Array
(
[id] => 10270893
[patent_doc_number] => 20150155889
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-06-04
[patent_title] => 'Selective merge and partial reuse LDPC (Low Density Parity Check) code construction for limited number of layers Belief Propagation (BP) decoding'
[patent_app_type] => utility
[patent_app_number] => 14/614521
[patent_app_country] => US
[patent_app_date] => 2015-02-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 32
[patent_figures_cnt] => 32
[patent_no_of_words] => 10961
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14614521
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/614521 | Selective merge and partial reuse LDPC (Low Density Parity Check) code construction for limited number of layers Belief Propagation (BP) decoding | Feb 4, 2015 | Abandoned |
Array
(
[id] => 10250041
[patent_doc_number] => 20150135037
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-05-14
[patent_title] => 'APPARATUSES AND METHODS INCLUDING ERROR CORRECTION CODE ORGANIZATION'
[patent_app_type] => utility
[patent_app_number] => 14/600800
[patent_app_country] => US
[patent_app_date] => 2015-01-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 10171
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14600800
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/600800 | Apparatuses and methods including error correction code organization | Jan 19, 2015 | Issued |
Array
(
[id] => 10228122
[patent_doc_number] => 20150113115
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-04-23
[patent_title] => 'UPDATING ERROR RECOVERY INFORMATION IN A DISPERSED STORAGE NETWORK'
[patent_app_type] => utility
[patent_app_number] => 14/587948
[patent_app_country] => US
[patent_app_date] => 2014-12-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 31
[patent_figures_cnt] => 31
[patent_no_of_words] => 31967
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14587948
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/587948 | Updating error recovery information in a dispersed storage network | Dec 30, 2014 | Issued |
Array
(
[id] => 10681385
[patent_doc_number] => 20160027530
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-01-28
[patent_title] => 'SEMICONDUCTOR MEMORY APPARATUS'
[patent_app_type] => utility
[patent_app_number] => 14/526733
[patent_app_country] => US
[patent_app_date] => 2014-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5338
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14526733
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/526733 | SEMICONDUCTOR MEMORY APPARATUS | Oct 28, 2014 | Abandoned |
Array
(
[id] => 9866750
[patent_doc_number] => 20150046769
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-02-12
[patent_title] => 'PRE-FETCHING DATA SEGMENTS STORED IN A DISPERSED STORAGE NETWORK'
[patent_app_type] => utility
[patent_app_number] => 14/524037
[patent_app_country] => US
[patent_app_date] => 2014-10-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 31
[patent_figures_cnt] => 31
[patent_no_of_words] => 31983
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14524037
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/524037 | Pre-fetching data segments stored in a dispersed storage network | Oct 26, 2014 | Issued |
Array
(
[id] => 10479200
[patent_doc_number] => 20150364217
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-12-17
[patent_title] => 'SEMICONDUCTOR DEVICE AND OPERATION METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 14/523579
[patent_app_country] => US
[patent_app_date] => 2014-10-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5902
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14523579
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/523579 | Semiconductor device and operation method thereof | Oct 23, 2014 | Issued |
Array
(
[id] => 11876222
[patent_doc_number] => 09748002
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-08-29
[patent_title] => 'System-in-package module with memory'
[patent_app_type] => utility
[patent_app_number] => 14/522567
[patent_app_country] => US
[patent_app_date] => 2014-10-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 5908
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14522567
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/522567 | System-in-package module with memory | Oct 22, 2014 | Issued |
Array
(
[id] => 10771061
[patent_doc_number] => 20160117217
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-04-28
[patent_title] => 'APPARATUS AND A METHOD OF DETECTING ERRORS ON REGISTERS'
[patent_app_type] => utility
[patent_app_number] => 14/521333
[patent_app_country] => US
[patent_app_date] => 2014-10-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2511
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14521333
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/521333 | Apparatus and a method of detecting errors on registers | Oct 21, 2014 | Issued |
Array
(
[id] => 11659087
[patent_doc_number] => 09672089
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-06-06
[patent_title] => 'Method to determine BER (bit error rate) from an eye diagram'
[patent_app_type] => utility
[patent_app_number] => 14/519703
[patent_app_country] => US
[patent_app_date] => 2014-10-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 18
[patent_no_of_words] => 11946
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 146
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14519703
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/519703 | Method to determine BER (bit error rate) from an eye diagram | Oct 20, 2014 | Issued |
Array
(
[id] => 11416547
[patent_doc_number] => 09563373
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-02-07
[patent_title] => 'Detecting error count deviations for non-volatile memory blocks for advanced non-volatile memory block management'
[patent_app_type] => utility
[patent_app_number] => 14/520276
[patent_app_country] => US
[patent_app_date] => 2014-10-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 8819
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14520276
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/520276 | Detecting error count deviations for non-volatile memory blocks for advanced non-volatile memory block management | Oct 20, 2014 | Issued |
Array
(
[id] => 10228353
[patent_doc_number] => 20150113346
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-04-23
[patent_title] => 'ELECTRONIC CIRCUIT HAVING SERIAL LATCH SCAN CHAINS'
[patent_app_type] => utility
[patent_app_number] => 14/520115
[patent_app_country] => US
[patent_app_date] => 2014-10-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 6755
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14520115
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/520115 | Electronic circuit having serial latch scan chains | Oct 20, 2014 | Issued |
Array
(
[id] => 10763359
[patent_doc_number] => 20160109514
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-04-21
[patent_title] => 'STRUCTURAL TESTING OF INTEGRATED CIRCUITS'
[patent_app_type] => utility
[patent_app_number] => 14/514402
[patent_app_country] => US
[patent_app_date] => 2014-10-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5149
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14514402
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/514402 | Structural testing of integrated circuits | Oct 14, 2014 | Issued |
Array
(
[id] => 11659869
[patent_doc_number] => 09672880
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-06-06
[patent_title] => 'Radiation upset detection'
[patent_app_type] => utility
[patent_app_number] => 14/511709
[patent_app_country] => US
[patent_app_date] => 2014-10-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 11471
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 174
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14511709
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/511709 | Radiation upset detection | Oct 9, 2014 | Issued |
Array
(
[id] => 10177822
[patent_doc_number] => 09208026
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-12-08
[patent_title] => 'Utilizing a local area network memory and a dispersed storage network memory to access data'
[patent_app_type] => utility
[patent_app_number] => 14/505835
[patent_app_country] => US
[patent_app_date] => 2014-10-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 21
[patent_no_of_words] => 19480
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 242
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14505835
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/505835 | Utilizing a local area network memory and a dispersed storage network memory to access data | Oct 2, 2014 | Issued |