Search

Kevin J. Quarterman

Examiner (ID: 12524, Phone: (571)272-2461 , Office: P/2879 )

Most Active Art Unit
2879
Art Unit(s)
2875, 2879, 2889
Total Applications
1644
Issued Applications
1325
Pending Applications
104
Abandoned Applications
237

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3873093 [patent_doc_number] => 05824582 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-20 [patent_title] => 'Stack DRAM cell manufacturing process with high capacitance capacitor' [patent_app_type] => 1 [patent_app_number] => 8/868607 [patent_app_country] => US [patent_app_date] => 1997-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 2779 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/824/05824582.pdf [firstpage_image] =>[orig_patent_app_number] => 868607 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/868607
Stack DRAM cell manufacturing process with high capacitance capacitor Jun 3, 1997 Issued
Array ( [id] => 3759631 [patent_doc_number] => 05843821 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-01 [patent_title] => 'Fabrication method for a cylindrical capacitor for a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/868605 [patent_app_country] => US [patent_app_date] => 1997-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 3678 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 382 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/843/05843821.pdf [firstpage_image] =>[orig_patent_app_number] => 868605 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/868605
Fabrication method for a cylindrical capacitor for a semiconductor device Jun 3, 1997 Issued
Array ( [id] => 4001105 [patent_doc_number] => 05858869 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-12 [patent_title] => 'Method for fabricating intermetal dielectric insulation using anisotropic plasma oxides and low dielectric constant polymers' [patent_app_type] => 1 [patent_app_number] => 8/868343 [patent_app_country] => US [patent_app_date] => 1997-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 4848 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/858/05858869.pdf [firstpage_image] =>[orig_patent_app_number] => 868343 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/868343
Method for fabricating intermetal dielectric insulation using anisotropic plasma oxides and low dielectric constant polymers Jun 2, 1997 Issued
Array ( [id] => 3760112 [patent_doc_number] => 05851885 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-22 [patent_title] => 'Manufacturing method for ROM components having a silicon controlled rectifier structure' [patent_app_type] => 1 [patent_app_number] => 8/866320 [patent_app_country] => US [patent_app_date] => 1997-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 3744 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 530 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/851/05851885.pdf [firstpage_image] =>[orig_patent_app_number] => 866320 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/866320
Manufacturing method for ROM components having a silicon controlled rectifier structure May 29, 1997 Issued
Array ( [id] => 3858803 [patent_doc_number] => 05792695 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-11 [patent_title] => 'Manufacturing method of a semiconductor eprom device' [patent_app_type] => 1 [patent_app_number] => 8/866425 [patent_app_country] => US [patent_app_date] => 1997-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 21 [patent_no_of_words] => 8342 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 520 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/792/05792695.pdf [firstpage_image] =>[orig_patent_app_number] => 866425 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/866425
Manufacturing method of a semiconductor eprom device May 29, 1997 Issued
Array ( [id] => 4031322 [patent_doc_number] => 05907774 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-25 [patent_title] => 'Corrugated post capacitor and method of fabricating using selective silicon deposition' [patent_app_type] => 1 [patent_app_number] => 8/865445 [patent_app_country] => US [patent_app_date] => 1997-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 3042 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/907/05907774.pdf [firstpage_image] =>[orig_patent_app_number] => 865445 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/865445
Corrugated post capacitor and method of fabricating using selective silicon deposition May 28, 1997 Issued
Array ( [id] => 3806145 [patent_doc_number] => 05854110 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-29 [patent_title] => 'Process fabricating semiconductor device having two ion-implantations carried out by using a shared photo-resist mask' [patent_app_type] => 1 [patent_app_number] => 8/864429 [patent_app_country] => US [patent_app_date] => 1997-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4080 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 310 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/854/05854110.pdf [firstpage_image] =>[orig_patent_app_number] => 864429 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/864429
Process fabricating semiconductor device having two ion-implantations carried out by using a shared photo-resist mask May 27, 1997 Issued
Array ( [id] => 4222046 [patent_doc_number] => 06010931 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-04 [patent_title] => 'Planarization technique for DRAM cell capacitor electrode' [patent_app_type] => 1 [patent_app_number] => 8/864299 [patent_app_country] => US [patent_app_date] => 1997-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 6200 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 297 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/010/06010931.pdf [firstpage_image] =>[orig_patent_app_number] => 864299 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/864299
Planarization technique for DRAM cell capacitor electrode May 27, 1997 Issued
Array ( [id] => 3975880 [patent_doc_number] => 05937271 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'Method for manufacturing a thin film actuated mirror array' [patent_app_type] => 1 [patent_app_number] => 8/862246 [patent_app_country] => US [patent_app_date] => 1997-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 3315 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/937/05937271.pdf [firstpage_image] =>[orig_patent_app_number] => 862246 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/862246
Method for manufacturing a thin film actuated mirror array May 22, 1997 Issued
Array ( [id] => 3804588 [patent_doc_number] => 05830792 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-03 [patent_title] => 'Method of making a stack capacitor in a DRAM cell' [patent_app_type] => 1 [patent_app_number] => 8/859855 [patent_app_country] => US [patent_app_date] => 1997-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2523 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/830/05830792.pdf [firstpage_image] =>[orig_patent_app_number] => 859855 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/859855
Method of making a stack capacitor in a DRAM cell May 20, 1997 Issued
Array ( [id] => 4038885 [patent_doc_number] => 05926708 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-20 [patent_title] => 'Method for providing multiple gate oxide thicknesses on the same wafer' [patent_app_type] => 1 [patent_app_number] => 8/859588 [patent_app_country] => US [patent_app_date] => 1997-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2148 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/926/05926708.pdf [firstpage_image] =>[orig_patent_app_number] => 859588 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/859588
Method for providing multiple gate oxide thicknesses on the same wafer May 19, 1997 Issued
Array ( [id] => 3950398 [patent_doc_number] => 05899716 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-04 [patent_title] => 'Oxygen ion implantation procedure to increase the surface area of an STC structure' [patent_app_type] => 1 [patent_app_number] => 8/861313 [patent_app_country] => US [patent_app_date] => 1997-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2794 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/899/05899716.pdf [firstpage_image] =>[orig_patent_app_number] => 861313 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/861313
Oxygen ion implantation procedure to increase the surface area of an STC structure May 18, 1997 Issued
Array ( [id] => 3760097 [patent_doc_number] => 05851884 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-22 [patent_title] => 'Structure and manufacturing method for ROM' [patent_app_type] => 1 [patent_app_number] => 8/857857 [patent_app_country] => US [patent_app_date] => 1997-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 2557 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/851/05851884.pdf [firstpage_image] =>[orig_patent_app_number] => 857857 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/857857
Structure and manufacturing method for ROM May 15, 1997 Issued
Array ( [id] => 4046489 [patent_doc_number] => 05869373 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-09 [patent_title] => 'Nand-structured and amorphous silicon based read-only memory device and method of fabricating the same' [patent_app_type] => 1 [patent_app_number] => 8/857859 [patent_app_country] => US [patent_app_date] => 1997-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 4366 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 312 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/869/05869373.pdf [firstpage_image] =>[orig_patent_app_number] => 857859 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/857859
Nand-structured and amorphous silicon based read-only memory device and method of fabricating the same May 15, 1997 Issued
Array ( [id] => 3858729 [patent_doc_number] => 05792690 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-11 [patent_title] => 'Method of fabricating a DRAM cell with an area equal to four times the used minimum feature' [patent_app_type] => 1 [patent_app_number] => 8/856777 [patent_app_country] => US [patent_app_date] => 1997-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 2811 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 540 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/792/05792690.pdf [firstpage_image] =>[orig_patent_app_number] => 856777 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/856777
Method of fabricating a DRAM cell with an area equal to four times the used minimum feature May 14, 1997 Issued
Array ( [id] => 4106734 [patent_doc_number] => 06022787 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-08 [patent_title] => 'Method of making a structure for providing signal isolation and decoupling in an integrated circuit device' [patent_app_type] => 1 [patent_app_number] => 8/847275 [patent_app_country] => US [patent_app_date] => 1997-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 17 [patent_no_of_words] => 5926 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/022/06022787.pdf [firstpage_image] =>[orig_patent_app_number] => 847275 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/847275
Method of making a structure for providing signal isolation and decoupling in an integrated circuit device Apr 30, 1997 Issued
Array ( [id] => 3943526 [patent_doc_number] => 05976930 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Method for forming gate segments for an integrated circuit' [patent_app_type] => 1 [patent_app_number] => 8/842971 [patent_app_country] => US [patent_app_date] => 1997-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 27 [patent_no_of_words] => 5334 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/976/05976930.pdf [firstpage_image] =>[orig_patent_app_number] => 842971 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/842971
Method for forming gate segments for an integrated circuit Apr 24, 1997 Issued
Array ( [id] => 4113591 [patent_doc_number] => 06046064 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-04 [patent_title] => 'Method for fabricating chemical semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/841723 [patent_app_country] => US [patent_app_date] => 1997-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 20 [patent_no_of_words] => 2966 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/046/06046064.pdf [firstpage_image] =>[orig_patent_app_number] => 841723 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/841723
Method for fabricating chemical semiconductor device Apr 23, 1997 Issued
Array ( [id] => 3760083 [patent_doc_number] => 05851883 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-22 [patent_title] => 'High density integrated circuit process' [patent_app_type] => 1 [patent_app_number] => 8/844975 [patent_app_country] => US [patent_app_date] => 1997-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 4748 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 360 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/851/05851883.pdf [firstpage_image] =>[orig_patent_app_number] => 844975 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/844975
High density integrated circuit process Apr 22, 1997 Issued
Array ( [id] => 3858832 [patent_doc_number] => 05792697 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-11 [patent_title] => 'Method for fabricating a multi-stage ROM' [patent_app_type] => 1 [patent_app_number] => 8/838979 [patent_app_country] => US [patent_app_date] => 1997-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 1813 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/792/05792697.pdf [firstpage_image] =>[orig_patent_app_number] => 838979 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/838979
Method for fabricating a multi-stage ROM Apr 22, 1997 Issued
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