Search

Kevin Ky

Examiner (ID: 583, Phone: (571)272-7648 , Office: P/2676 )

Most Active Art Unit
2669
Art Unit(s)
2676, 2669, 2671, 2661
Total Applications
707
Issued Applications
532
Pending Applications
88
Abandoned Applications
126

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11533402 [patent_doc_number] => 20170093382 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-30 [patent_title] => 'APPARATUS COMPRISING AN OSCILLATOR CIRCUIT, USE OF SUCH AN APPARATUS IN A RADIATION FIELD AS WELL AS METHOD FOR OPERATING SUCH AN APPARATUS IN A RADIATION FIELD' [patent_app_type] => utility [patent_app_number] => 15/272202 [patent_app_country] => US [patent_app_date] => 2016-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 11340 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15272202 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/272202
APPARATUS COMPRISING AN OSCILLATOR CIRCUIT, USE OF SUCH AN APPARATUS IN A RADIATION FIELD AS WELL AS METHOD FOR OPERATING SUCH AN APPARATUS IN A RADIATION FIELD Sep 20, 2016 Abandoned
Array ( [id] => 12295791 [patent_doc_number] => 09935619 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-03 [patent_title] => Semiconductor device and communication module [patent_app_type] => utility [patent_app_number] => 15/252940 [patent_app_country] => US [patent_app_date] => 2016-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3512 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 350 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15252940 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/252940
Semiconductor device and communication module Aug 30, 2016 Issued
Array ( [id] => 11967908 [patent_doc_number] => 20170272061 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-21 [patent_title] => 'VOLTAGE CLAMPING CIRCUIT' [patent_app_type] => utility [patent_app_number] => 15/251710 [patent_app_country] => US [patent_app_date] => 2016-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7983 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15251710 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/251710
VOLTAGE CLAMPING CIRCUIT Aug 29, 2016 Abandoned
Array ( [id] => 11898818 [patent_doc_number] => 09768765 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-19 [patent_title] => 'Gate control circuit and power supply circuit' [patent_app_type] => utility [patent_app_number] => 15/250569 [patent_app_country] => US [patent_app_date] => 2016-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8669 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15250569 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/250569
Gate control circuit and power supply circuit Aug 28, 2016 Issued
Array ( [id] => 11984508 [patent_doc_number] => 20170288663 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-05 [patent_title] => 'METHODS AND APPARATUS FOR LEVEL-SHIFTING HIGH SPEED SERIAL DATA WITH LOW POWER CONSUMPTION' [patent_app_type] => utility [patent_app_number] => 15/248173 [patent_app_country] => US [patent_app_date] => 2016-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4819 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15248173 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/248173
Methods and apparatus for level-shifting high speed serial data with low power consumption Aug 25, 2016 Issued
Array ( [id] => 13258431 [patent_doc_number] => 10141916 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-27 [patent_title] => High-speed flip-flop semiconductor device [patent_app_type] => utility [patent_app_number] => 15/245239 [patent_app_country] => US [patent_app_date] => 2016-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 12101 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15245239 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/245239
High-speed flip-flop semiconductor device Aug 23, 2016 Issued
Array ( [id] => 11340530 [patent_doc_number] => 20160366285 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-15 [patent_title] => 'BILLING ENGINE AND METHOD OF USE' [patent_app_type] => utility [patent_app_number] => 15/246165 [patent_app_country] => US [patent_app_date] => 2016-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 17012 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15246165 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/246165
Billing engine and method of use Aug 23, 2016 Issued
Array ( [id] => 11811852 [patent_doc_number] => 09716430 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-07-25 [patent_title] => 'Methods and circuitry for sampling a signal' [patent_app_type] => utility [patent_app_number] => 15/245902 [patent_app_country] => US [patent_app_date] => 2016-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 9731 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15245902 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/245902
Methods and circuitry for sampling a signal Aug 23, 2016 Issued
Array ( [id] => 11476586 [patent_doc_number] => 20170063369 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-02 [patent_title] => 'Methods and Apparatus for a Configurable High-Side NMOS Gate Control with Improved Gate to Source Voltage Regulation' [patent_app_type] => utility [patent_app_number] => 15/244814 [patent_app_country] => US [patent_app_date] => 2016-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5144 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15244814 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/244814
Methods and apparatus for a configurable high-side NMOS gate control with improved gate to source voltage regulation Aug 22, 2016 Issued
Array ( [id] => 11754121 [patent_doc_number] => 09712147 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-18 [patent_title] => 'Method for driving a transistor device and electronic circuit' [patent_app_type] => utility [patent_app_number] => 15/242342 [patent_app_country] => US [patent_app_date] => 2016-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 5763 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15242342 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/242342
Method for driving a transistor device and electronic circuit Aug 18, 2016 Issued
Array ( [id] => 12955492 [patent_doc_number] => 09837994 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-12-05 [patent_title] => Stacked delay element and method of assembling same [patent_app_type] => utility [patent_app_number] => 15/241214 [patent_app_country] => US [patent_app_date] => 2016-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 5279 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15241214 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/241214
Stacked delay element and method of assembling same Aug 18, 2016 Issued
Array ( [id] => 15377175 [patent_doc_number] => 10530320 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-07 [patent_title] => Attenuator de-Qing loss improvement and phase balance [patent_app_type] => utility [patent_app_number] => 15/212025 [patent_app_country] => US [patent_app_date] => 2016-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 3508 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15212025 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/212025
Attenuator de-Qing loss improvement and phase balance Jul 14, 2016 Issued
Array ( [id] => 13696397 [patent_doc_number] => 20170359153 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-14 [patent_title] => MEASURING DELAY LINE LINEARITY CHARACTERISTICS [patent_app_type] => utility [patent_app_number] => 15/182567 [patent_app_country] => US [patent_app_date] => 2016-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5809 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15182567 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/182567
MEASURING DELAY LINE LINEARITY CHARACTERISTICS Jun 13, 2016 Abandoned
Array ( [id] => 15201605 [patent_doc_number] => 10498314 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-03 [patent_title] => Vectored flip-flop [patent_app_type] => utility [patent_app_number] => 15/178294 [patent_app_country] => US [patent_app_date] => 2016-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7504 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15178294 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/178294
Vectored flip-flop Jun 8, 2016 Issued
Array ( [id] => 12694711 [patent_doc_number] => 20180123403 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-03 [patent_title] => LOCATING POWER RECEIVERS [patent_app_type] => utility [patent_app_number] => 15/574667 [patent_app_country] => US [patent_app_date] => 2016-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11907 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15574667 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/574667
Locating power receivers May 17, 2016 Issued
Array ( [id] => 11036903 [patent_doc_number] => 20160233859 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-11 [patent_title] => 'POWER SWITCHING SYSTEMS COMPRISING HIGH POWER E-MODE GaN TRANSISTORS AND DRIVER CIRCUITRY' [patent_app_type] => utility [patent_app_number] => 15/099459 [patent_app_country] => US [patent_app_date] => 2016-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6735 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15099459 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/099459
Power switching systems comprising high power e-mode GaN transistors and driver circuitry Apr 13, 2016 Issued
Array ( [id] => 12203136 [patent_doc_number] => 09906218 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-02-27 [patent_title] => 'Dual-gate transistor control based on calibration circuitry' [patent_app_type] => utility [patent_app_number] => 15/098165 [patent_app_country] => US [patent_app_date] => 2016-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 10055 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15098165 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/098165
Dual-gate transistor control based on calibration circuitry Apr 12, 2016 Issued
Array ( [id] => 11014880 [patent_doc_number] => 20160211833 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-21 [patent_title] => 'STITCHABLE GLOBAL CLOCK FOR 3D CHIPS' [patent_app_type] => utility [patent_app_number] => 15/085294 [patent_app_country] => US [patent_app_date] => 2016-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6337 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15085294 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/085294
Stitchable global clock for 3D chips Mar 29, 2016 Issued
Array ( [id] => 11007826 [patent_doc_number] => 20160204778 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-14 [patent_title] => 'TRANSMISSION CHANNEL FOR ULTRASOUND APPLICATIONS' [patent_app_type] => utility [patent_app_number] => 15/076211 [patent_app_country] => US [patent_app_date] => 2016-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9883 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15076211 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/076211
Transmission channel for ultrasound applications Mar 20, 2016 Issued
Array ( [id] => 10994085 [patent_doc_number] => 20160191031 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-30 [patent_title] => 'DYNAMIC MARGIN TUNING FOR CONTROLLING CUSTOM CIRCUITS AND MEMORIES' [patent_app_type] => utility [patent_app_number] => 15/065952 [patent_app_country] => US [patent_app_date] => 2016-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4737 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15065952 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/065952
Dynamic margin tuning for controlling custom circuits and memories Mar 9, 2016 Issued
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