Search

Kevin L. Ellis

Examiner (ID: 15401)

Most Active Art Unit
2188
Art Unit(s)
2185, 2753, 2188, 2187, 2312, 2751, 2186, 2117
Total Applications
728
Issued Applications
637
Pending Applications
23
Abandoned Applications
67

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1501562 [patent_doc_number] => 06405291 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-11 [patent_title] => 'Predictive snooping of cache memory for master-initiated accesses' [patent_app_type] => B1 [patent_app_number] => 09/631564 [patent_app_country] => US [patent_app_date] => 2000-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 18574 [patent_no_of_claims] => 89 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/405/06405291.pdf [firstpage_image] =>[orig_patent_app_number] => 09631564 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/631564
Predictive snooping of cache memory for master-initiated accesses Aug 1, 2000 Issued
Array ( [id] => 1533127 [patent_doc_number] => 06480933 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-12 [patent_title] => 'Disk cache device and method for secure writing of hard disks in mass memory subsystems' [patent_app_type] => B1 [patent_app_number] => 09/582875 [patent_app_country] => US [patent_app_date] => 2000-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 5709 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/480/06480933.pdf [firstpage_image] =>[orig_patent_app_number] => 09582875 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/582875
Disk cache device and method for secure writing of hard disks in mass memory subsystems Jul 5, 2000 Issued
Array ( [id] => 1366545 [patent_doc_number] => 06584552 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-24 [patent_title] => 'Recording/reproducing apparatus, program recorded medium, recorded medium, cache device, and transmitter' [patent_app_type] => B1 [patent_app_number] => 09/582800 [patent_app_country] => US [patent_app_date] => 2000-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 54 [patent_figures_cnt] => 55 [patent_no_of_words] => 50346 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/584/06584552.pdf [firstpage_image] =>[orig_patent_app_number] => 09582800 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/582800
Recording/reproducing apparatus, program recorded medium, recorded medium, cache device, and transmitter Jun 29, 2000 Issued
Array ( [id] => 1291854 [patent_doc_number] => 06643746 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-04 [patent_title] => 'Optimal multi-channel memory controller system' [patent_app_type] => B1 [patent_app_number] => 09/582575 [patent_app_country] => US [patent_app_date] => 2000-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4643 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/643/06643746.pdf [firstpage_image] =>[orig_patent_app_number] => 09582575 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/582575
Optimal multi-channel memory controller system Jun 21, 2000 Issued
Array ( [id] => 1429311 [patent_doc_number] => 06530004 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-04 [patent_title] => 'Efficient fault-tolerant preservation of data integrity during dynamic RAID data migration' [patent_app_type] => B1 [patent_app_number] => 09/597972 [patent_app_country] => US [patent_app_date] => 2000-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 48 [patent_no_of_words] => 7575 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/530/06530004.pdf [firstpage_image] =>[orig_patent_app_number] => 09597972 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/597972
Efficient fault-tolerant preservation of data integrity during dynamic RAID data migration Jun 19, 2000 Issued
Array ( [id] => 1431099 [patent_doc_number] => 06507903 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-14 [patent_title] => 'High performance non-blocking parallel storage manager for parallel software executing on coordinates' [patent_app_type] => B1 [patent_app_number] => 09/597525 [patent_app_country] => US [patent_app_date] => 2000-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 7332 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/507/06507903.pdf [firstpage_image] =>[orig_patent_app_number] => 09597525 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/597525
High performance non-blocking parallel storage manager for parallel software executing on coordinates Jun 19, 2000 Issued
Array ( [id] => 1415721 [patent_doc_number] => 06549986 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-15 [patent_title] => 'Low power instruction cache' [patent_app_type] => B1 [patent_app_number] => 09/598063 [patent_app_country] => US [patent_app_date] => 2000-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 6813 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/549/06549986.pdf [firstpage_image] =>[orig_patent_app_number] => 09598063 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/598063
Low power instruction cache Jun 19, 2000 Issued
Array ( [id] => 7645889 [patent_doc_number] => 06477634 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-05 [patent_title] => 'Physical pages de-allocation method for virtual addressing machine' [patent_app_type] => B1 [patent_app_number] => 09/597071 [patent_app_country] => US [patent_app_date] => 2000-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4340 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 11 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/477/06477634.pdf [firstpage_image] =>[orig_patent_app_number] => 09597071 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/597071
Physical pages de-allocation method for virtual addressing machine Jun 19, 2000 Issued
Array ( [id] => 1381786 [patent_doc_number] => 06574720 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-03 [patent_title] => 'System for maintaining a buffer pool' [patent_app_type] => B1 [patent_app_number] => 09/595667 [patent_app_country] => US [patent_app_date] => 2000-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6166 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/574/06574720.pdf [firstpage_image] =>[orig_patent_app_number] => 09595667 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/595667
System for maintaining a buffer pool Jun 18, 2000 Issued
Array ( [id] => 1337233 [patent_doc_number] => 06604187 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-08-05 [patent_title] => 'Providing global translations with address space numbers' [patent_app_type] => B1 [patent_app_number] => 09/596636 [patent_app_country] => US [patent_app_date] => 2000-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8919 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/604/06604187.pdf [firstpage_image] =>[orig_patent_app_number] => 09596636 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/596636
Providing global translations with address space numbers Jun 18, 2000 Issued
Array ( [id] => 1460049 [patent_doc_number] => 06463518 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-08 [patent_title] => 'Generation of memory addresses for accessing a memory utilizing scheme registers' [patent_app_type] => B1 [patent_app_number] => 09/596321 [patent_app_country] => US [patent_app_date] => 2000-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 6433 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/463/06463518.pdf [firstpage_image] =>[orig_patent_app_number] => 09596321 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/596321
Generation of memory addresses for accessing a memory utilizing scheme registers Jun 18, 2000 Issued
Array ( [id] => 1381490 [patent_doc_number] => 06574704 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-03 [patent_title] => 'Information storage management device and method, control device and method' [patent_app_type] => B1 [patent_app_number] => 09/593950 [patent_app_country] => US [patent_app_date] => 2000-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7187 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/574/06574704.pdf [firstpage_image] =>[orig_patent_app_number] => 09593950 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/593950
Information storage management device and method, control device and method Jun 18, 2000 Issued
Array ( [id] => 1385851 [patent_doc_number] => 06571316 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-27 [patent_title] => 'Cache memory array for multiple address spaces' [patent_app_type] => B1 [patent_app_number] => 09/595077 [patent_app_country] => US [patent_app_date] => 2000-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2376 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/571/06571316.pdf [firstpage_image] =>[orig_patent_app_number] => 09595077 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/595077
Cache memory array for multiple address spaces Jun 15, 2000 Issued
Array ( [id] => 1401063 [patent_doc_number] => 06564297 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-13 [patent_title] => 'Compiler-based cache line optimization' [patent_app_type] => B1 [patent_app_number] => 09/594430 [patent_app_country] => US [patent_app_date] => 2000-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 7082 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/564/06564297.pdf [firstpage_image] =>[orig_patent_app_number] => 09594430 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/594430
Compiler-based cache line optimization Jun 14, 2000 Issued
Array ( [id] => 1456800 [patent_doc_number] => 06457115 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-24 [patent_title] => 'Apparatus and method for generating 64 bit addresses using a 32 bit adder' [patent_app_type] => B1 [patent_app_number] => 09/595299 [patent_app_country] => US [patent_app_date] => 2000-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 10267 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/457/06457115.pdf [firstpage_image] =>[orig_patent_app_number] => 09595299 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/595299
Apparatus and method for generating 64 bit addresses using a 32 bit adder Jun 14, 2000 Issued
Array ( [id] => 1429886 [patent_doc_number] => 06510508 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-21 [patent_title] => 'Translation lookaside buffer flush filter' [patent_app_type] => B1 [patent_app_number] => 09/595597 [patent_app_country] => US [patent_app_date] => 2000-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 8628 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/510/06510508.pdf [firstpage_image] =>[orig_patent_app_number] => 09595597 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/595597
Translation lookaside buffer flush filter Jun 14, 2000 Issued
Array ( [id] => 1460045 [patent_doc_number] => 06463517 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-08 [patent_title] => 'Apparatus and method for generating virtual addresses for different memory models' [patent_app_type] => B1 [patent_app_number] => 09/595576 [patent_app_country] => US [patent_app_date] => 2000-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 10305 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/463/06463517.pdf [firstpage_image] =>[orig_patent_app_number] => 09595576 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/595576
Apparatus and method for generating virtual addresses for different memory models Jun 14, 2000 Issued
Array ( [id] => 1425318 [patent_doc_number] => 06535969 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-18 [patent_title] => 'Method and apparatus for allocating free memory' [patent_app_type] => B1 [patent_app_number] => 09/594376 [patent_app_country] => US [patent_app_date] => 2000-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3080 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/535/06535969.pdf [firstpage_image] =>[orig_patent_app_number] => 09594376 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/594376
Method and apparatus for allocating free memory Jun 14, 2000 Issued
Array ( [id] => 1462433 [patent_doc_number] => 06427195 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-30 [patent_title] => 'Thread local cache memory allocator in a multitasking operating system' [patent_app_type] => B1 [patent_app_number] => 09/592781 [patent_app_country] => US [patent_app_date] => 2000-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5570 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/427/06427195.pdf [firstpage_image] =>[orig_patent_app_number] => 09592781 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/592781
Thread local cache memory allocator in a multitasking operating system Jun 12, 2000 Issued
Array ( [id] => 1557582 [patent_doc_number] => 06401187 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-04 [patent_title] => 'Memory access optimizing method' [patent_app_type] => B1 [patent_app_number] => 09/581361 [patent_app_country] => US [patent_app_date] => 2000-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 28 [patent_no_of_words] => 13136 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/401/06401187.pdf [firstpage_image] =>[orig_patent_app_number] => 09581361 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/581361
Memory access optimizing method Jun 11, 2000 Issued
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