Search

Kevin L. Ellis

Examiner (ID: 15401)

Most Active Art Unit
2188
Art Unit(s)
2185, 2753, 2188, 2187, 2312, 2751, 2186, 2117
Total Applications
728
Issued Applications
637
Pending Applications
23
Abandoned Applications
67

Applications

Application numberTitle of the applicationFiling DateStatus
08/438550 METHOD AND APPARATUS FOR MANAGING SNOOP REQUESTS USING SNOOP ADVISORY CELLS May 9, 1995 Abandoned
Array ( [id] => 3707749 [patent_doc_number] => 05680576 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-21 [patent_title] => 'Directory-based coherence protocol allowing efficient dropping of clean-exclusive data' [patent_app_type] => 1 [patent_app_number] => 8/435460 [patent_app_country] => US [patent_app_date] => 1995-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 9642 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/680/05680576.pdf [firstpage_image] =>[orig_patent_app_number] => 435460 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/435460
Directory-based coherence protocol allowing efficient dropping of clean-exclusive data May 4, 1995 Issued
08/433150 CACHE COHERENCY WHRER MULTIPLE PROCESSORS MAY ACCESS THE SAME DATA OVER INDEPENDENT ACCESS PATHS May 2, 1995 Abandoned
08/431601 A PROCESSOR HAVING A PLURALITY OF PIPELINES AND A MECHANISM FOR MAINTAINING COHERENCY AMONG REGISTER VALUES IN THE PIPELINES Apr 30, 1995 Abandoned
Array ( [id] => 3700411 [patent_doc_number] => 05696936 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-09 [patent_title] => 'Low latency message processor interface using memory mapped Read/Write Windows' [patent_app_type] => 1 [patent_app_number] => 8/428054 [patent_app_country] => US [patent_app_date] => 1995-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5290 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/696/05696936.pdf [firstpage_image] =>[orig_patent_app_number] => 428054 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/428054
Low latency message processor interface using memory mapped Read/Write Windows Apr 24, 1995 Issued
Array ( [id] => 3705981 [patent_doc_number] => 05651137 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-22 [patent_title] => 'Scalable cache attributes for an input/output bus' [patent_app_type] => 1 [patent_app_number] => 8/420494 [patent_app_country] => US [patent_app_date] => 1995-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 13057 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/651/05651137.pdf [firstpage_image] =>[orig_patent_app_number] => 420494 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/420494
Scalable cache attributes for an input/output bus Apr 11, 1995 Issued
Array ( [id] => 3673166 [patent_doc_number] => 05649150 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-15 [patent_title] => 'Scannable last-in-first-out register stack' [patent_app_type] => 1 [patent_app_number] => 8/420962 [patent_app_country] => US [patent_app_date] => 1995-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 3555 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/649/05649150.pdf [firstpage_image] =>[orig_patent_app_number] => 420962 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/420962
Scannable last-in-first-out register stack Apr 11, 1995 Issued
08/414670 COMPUTER ARCHITECTURE INCORPORATING PROCESSOR CLUSTERS AND HIERARCHICAL CACHE MEMORIES Mar 30, 1995 Abandoned
Array ( [id] => 3701153 [patent_doc_number] => 05692149 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-25 [patent_title] => 'Block replacement method in cache only memory architecture multiprocessor' [patent_app_type] => 1 [patent_app_number] => 8/405335 [patent_app_country] => US [patent_app_date] => 1995-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6111 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 388 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/692/05692149.pdf [firstpage_image] =>[orig_patent_app_number] => 405335 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/405335
Block replacement method in cache only memory architecture multiprocessor Mar 15, 1995 Issued
Array ( [id] => 4006953 [patent_doc_number] => 05960461 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Multiprocessor digital data processing system/shared memory multiprocessor system and method of operation' [patent_app_type] => 1 [patent_app_number] => 8/403308 [patent_app_country] => US [patent_app_date] => 1995-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 75 [patent_figures_cnt] => 14 [patent_no_of_words] => 18819 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/960/05960461.pdf [firstpage_image] =>[orig_patent_app_number] => 403308 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/403308
Multiprocessor digital data processing system/shared memory multiprocessor system and method of operation Mar 13, 1995 Issued
Array ( [id] => 3633504 [patent_doc_number] => 05615355 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-25 [patent_title] => 'Method and apparatus for buffering a user application from the timing requirements of a DRAM' [patent_app_type] => 1 [patent_app_number] => 8/401329 [patent_app_country] => US [patent_app_date] => 1995-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5671 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/615/05615355.pdf [firstpage_image] =>[orig_patent_app_number] => 401329 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/401329
Method and apparatus for buffering a user application from the timing requirements of a DRAM Mar 8, 1995 Issued
Array ( [id] => 3843597 [patent_doc_number] => 05784712 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-21 [patent_title] => 'Method and apparatus for locally generating addressing information for a memory access' [patent_app_type] => 1 [patent_app_number] => 8/396677 [patent_app_country] => US [patent_app_date] => 1995-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 27 [patent_no_of_words] => 20769 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/784/05784712.pdf [firstpage_image] =>[orig_patent_app_number] => 396677 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/396677
Method and apparatus for locally generating addressing information for a memory access Feb 28, 1995 Issued
Array ( [id] => 3716561 [patent_doc_number] => 05675769 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-07 [patent_title] => 'Method for manipulating disk partitions' [patent_app_type] => 1 [patent_app_number] => 8/393805 [patent_app_country] => US [patent_app_date] => 1995-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 17293 [patent_no_of_claims] => 67 [patent_no_of_ind_claims] => 16 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/675/05675769.pdf [firstpage_image] =>[orig_patent_app_number] => 393805 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/393805
Method for manipulating disk partitions Feb 22, 1995 Issued
Array ( [id] => 3900934 [patent_doc_number] => 05749093 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-05 [patent_title] => 'Enhanced information processing system using cache memory indication during DMA accessing' [patent_app_type] => 1 [patent_app_number] => 8/389080 [patent_app_country] => US [patent_app_date] => 1995-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2322 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/749/05749093.pdf [firstpage_image] =>[orig_patent_app_number] => 389080 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/389080
Enhanced information processing system using cache memory indication during DMA accessing Feb 13, 1995 Issued
08/381157 CACHE-MEMORY SYSTEM SUITABLE FOR PROCESSING DATA ARRAYED IN MULTIDIMENSIONAL SPACE Jan 30, 1995 Abandoned
Array ( [id] => 3707836 [patent_doc_number] => 05680581 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-21 [patent_title] => 'Microcomputer having a read protection circuit to secure the contents of an internal memory' [patent_app_type] => 1 [patent_app_number] => 8/364989 [patent_app_country] => US [patent_app_date] => 1994-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5480 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/680/05680581.pdf [firstpage_image] =>[orig_patent_app_number] => 364989 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/364989
Microcomputer having a read protection circuit to secure the contents of an internal memory Dec 27, 1994 Issued
Array ( [id] => 3635438 [patent_doc_number] => 05613085 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-18 [patent_title] => 'System for parallel striping of multiple ordered data strings onto a multi-unit DASD array for improved read and write parallelism' [patent_app_type] => 1 [patent_app_number] => 8/364572 [patent_app_country] => US [patent_app_date] => 1994-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 5716 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/613/05613085.pdf [firstpage_image] =>[orig_patent_app_number] => 364572 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/364572
System for parallel striping of multiple ordered data strings onto a multi-unit DASD array for improved read and write parallelism Dec 26, 1994 Issued
Array ( [id] => 3744166 [patent_doc_number] => 05636361 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-03 [patent_title] => 'Multi-processor computer system having dual memory subsytems for enabling concurrent memory access thereto by more than one processor' [patent_app_type] => 1 [patent_app_number] => 8/362389 [patent_app_country] => US [patent_app_date] => 1994-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 5511 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 323 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/636/05636361.pdf [firstpage_image] =>[orig_patent_app_number] => 362389 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/362389
Multi-processor computer system having dual memory subsytems for enabling concurrent memory access thereto by more than one processor Dec 21, 1994 Issued
08/356596 A REGISTER CACHE FOR PROVIDING REGISTER VALUES TO A COMPUTER PROCESSOR Dec 14, 1994 Abandoned
08/356479 METHOD OF CREATING AN INTERNALLY CONSISTENT COPY OF AN ACTIVELY UPDATED DATA SET WITHOUT SPECIALIZED CACHING HARDWARE Dec 14, 1994 Abandoned
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