Search

Kevin L. Ellis

Examiner (ID: 15401)

Most Active Art Unit
2188
Art Unit(s)
2185, 2753, 2188, 2187, 2312, 2751, 2186, 2117
Total Applications
728
Issued Applications
637
Pending Applications
23
Abandoned Applications
67

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3694569 [patent_doc_number] => 05634038 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-27 [patent_title] => 'Common memory protection system in a multiprocessor configuration using semaphore-flags stored at complementary addresses for enabling access to the memory' [patent_app_type] => 1 [patent_app_number] => 8/322345 [patent_app_country] => US [patent_app_date] => 1994-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5868 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/634/05634038.pdf [firstpage_image] =>[orig_patent_app_number] => 322345 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/322345
Common memory protection system in a multiprocessor configuration using semaphore-flags stored at complementary addresses for enabling access to the memory Oct 12, 1994 Issued
Array ( [id] => 3677667 [patent_doc_number] => 05668972 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-16 [patent_title] => 'Method and system for efficient miss sequence cache line allocation utilizing an allocation control cell state to enable a selected match line' [patent_app_type] => 1 [patent_app_number] => 8/319202 [patent_app_country] => US [patent_app_date] => 1994-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 7684 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/668/05668972.pdf [firstpage_image] =>[orig_patent_app_number] => 319202 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/319202
Method and system for efficient miss sequence cache line allocation utilizing an allocation control cell state to enable a selected match line Oct 4, 1994 Issued
Array ( [id] => 3660385 [patent_doc_number] => 05640534 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-17 [patent_title] => 'Method and system for concurrent access in a data cache array utilizing multiple match line selection paths' [patent_app_type] => 1 [patent_app_number] => 8/319332 [patent_app_country] => US [patent_app_date] => 1994-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 7743 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/640/05640534.pdf [firstpage_image] =>[orig_patent_app_number] => 319332 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/319332
Method and system for concurrent access in a data cache array utilizing multiple match line selection paths Oct 4, 1994 Issued
Array ( [id] => 3701014 [patent_doc_number] => 05644751 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-01 [patent_title] => 'Distributed file system (DFS) cache management based on file access characteristics' [patent_app_type] => 1 [patent_app_number] => 8/317981 [patent_app_country] => US [patent_app_date] => 1994-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 5942 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/644/05644751.pdf [firstpage_image] =>[orig_patent_app_number] => 317981 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/317981
Distributed file system (DFS) cache management based on file access characteristics Oct 2, 1994 Issued
Array ( [id] => 3669915 [patent_doc_number] => 05659709 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-19 [patent_title] => 'Write-back and snoop write-back buffer to prevent deadlock and to enhance performance in an in-order protocol multiprocessing bus' [patent_app_type] => 1 [patent_app_number] => 8/317297 [patent_app_country] => US [patent_app_date] => 1994-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 23 [patent_no_of_words] => 11375 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/659/05659709.pdf [firstpage_image] =>[orig_patent_app_number] => 317297 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/317297
Write-back and snoop write-back buffer to prevent deadlock and to enhance performance in an in-order protocol multiprocessing bus Oct 2, 1994 Issued
Array ( [id] => 3669901 [patent_doc_number] => 05659708 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-19 [patent_title] => 'Cache coherency in a multiprocessing system' [patent_app_type] => 1 [patent_app_number] => 8/317256 [patent_app_country] => US [patent_app_date] => 1994-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2869 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/659/05659708.pdf [firstpage_image] =>[orig_patent_app_number] => 317256 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/317256
Cache coherency in a multiprocessing system Oct 2, 1994 Issued
08/316550 METHOD AND APPARATUS FOR PROCERSSING MEMORY-TYPE INFORMATION WITHIN A MICROPROCESSOR Sep 29, 1994 Abandoned
08/314852 METHOD AND DATA STORAGE SYSTEM FOR STORING DATA IN BLOCKS WITHOUT FILE REALLOCATION BEFORE ERASURE Sep 28, 1994 Abandoned
Array ( [id] => 3566193 [patent_doc_number] => 05574884 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-12 [patent_title] => 'DRAM control circuit' [patent_app_type] => 1 [patent_app_number] => 8/302035 [patent_app_country] => US [patent_app_date] => 1994-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3422 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 339 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/574/05574884.pdf [firstpage_image] =>[orig_patent_app_number] => 302035 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/302035
DRAM control circuit Sep 8, 1994 Issued
Array ( [id] => 3893757 [patent_doc_number] => 05729715 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-17 [patent_title] => 'Filing system with multiple forms of storage' [patent_app_type] => 1 [patent_app_number] => 8/302942 [patent_app_country] => US [patent_app_date] => 1994-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 42 [patent_no_of_words] => 12062 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/729/05729715.pdf [firstpage_image] =>[orig_patent_app_number] => 302942 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/302942
Filing system with multiple forms of storage Sep 8, 1994 Issued
Array ( [id] => 3700321 [patent_doc_number] => 05696931 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-09 [patent_title] => 'Disc drive controller with apparatus and method for automatic transfer of cache data' [patent_app_type] => 1 [patent_app_number] => 8/303415 [patent_app_country] => US [patent_app_date] => 1994-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7052 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/696/05696931.pdf [firstpage_image] =>[orig_patent_app_number] => 303415 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/303415
Disc drive controller with apparatus and method for automatic transfer of cache data Sep 8, 1994 Issued
08/301482 INVAILD WRITE RECOVERY APPARATUS AND METHOD WITHIN CACHE MEMORY Sep 6, 1994 Abandoned
08/298987 COMPUTER SYSTEM PERMITTING MULTIPLE WRITE BUFFER READ-AROUNDS AND METHOD THEREFOR Aug 30, 1994 Abandoned
Array ( [id] => 3900893 [patent_doc_number] => 05749090 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-05 [patent_title] => 'Cache tag RAM having separate valid bit array with multiple step invalidation and method therefor' [patent_app_type] => 1 [patent_app_number] => 8/293625 [patent_app_country] => US [patent_app_date] => 1994-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4732 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 273 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/749/05749090.pdf [firstpage_image] =>[orig_patent_app_number] => 293625 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/293625
Cache tag RAM having separate valid bit array with multiple step invalidation and method therefor Aug 21, 1994 Issued
Array ( [id] => 3860177 [patent_doc_number] => 05848432 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-08 [patent_title] => 'Data processor with variable types of cache memories' [patent_app_type] => 1 [patent_app_number] => 8/281002 [patent_app_country] => US [patent_app_date] => 1994-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 55 [patent_no_of_words] => 23784 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/848/05848432.pdf [firstpage_image] =>[orig_patent_app_number] => 281002 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/281002
Data processor with variable types of cache memories Jul 26, 1994 Issued
08/274845 MONOLITHIC IMAGE DATA MEMORY SYSTEM AND ACCESS METHOD Jul 12, 1994 Abandoned
Array ( [id] => 3707703 [patent_doc_number] => 05680573 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-21 [patent_title] => 'Method of buffering data objects in a database' [patent_app_type] => 1 [patent_app_number] => 8/273867 [patent_app_country] => US [patent_app_date] => 1994-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9584 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/680/05680573.pdf [firstpage_image] =>[orig_patent_app_number] => 273867 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/273867
Method of buffering data objects in a database Jul 11, 1994 Issued
Array ( [id] => 3743835 [patent_doc_number] => 05666514 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-09 [patent_title] => 'Cache memory containing extra status bits to indicate memory regions where logging of data should occur' [patent_app_type] => 1 [patent_app_number] => 8/270655 [patent_app_country] => US [patent_app_date] => 1994-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 32 [patent_no_of_words] => 24174 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/666/05666514.pdf [firstpage_image] =>[orig_patent_app_number] => 270655 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/270655
Cache memory containing extra status bits to indicate memory regions where logging of data should occur Jun 30, 1994 Issued
08/261797 METHOD AND SYSTEM FOR MAINTAINING CONCURRENT DATA ACCESS DURING DEVICE UPGRADE Jun 19, 1994 Abandoned
Array ( [id] => 3718542 [patent_doc_number] => 05655101 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-05 [patent_title] => 'Accessing remote data objects in a distributed memory environment using parallel address locations at each local memory to reference a same data object' [patent_app_type] => 1 [patent_app_number] => 8/250202 [patent_app_country] => US [patent_app_date] => 1994-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4239 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/655/05655101.pdf [firstpage_image] =>[orig_patent_app_number] => 250202 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/250202
Accessing remote data objects in a distributed memory environment using parallel address locations at each local memory to reference a same data object May 26, 1994 Issued
Menu