Kevin L. Lee

Array ( [id] => 3918213 [patent_doc_number] => 06002161 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-14 [patent_title] => 'Semiconductor device having inductor element made of first conductive layer of spiral configuration electrically connected to second conductive layer of insular configuration' [patent_app_type] => 1 [patent_app_number] => 8/756536 [patent_app_country] => US [patent_app_date] => 1996-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 29 [patent_no_of_words] => 7319 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/002/06002161.pdf [firstpage_image] =>[orig_patent_app_number] => 756536 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3876842 [patent_doc_number] => 05728607 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-17 [patent_title] => 'Method of making a P-channel bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 8/754607 [patent_app_country] => US [patent_app_date] => 1996-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 56 [patent_no_of_words] => 2449 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 722 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/728/05728607.pdf [firstpage_image] =>[orig_patent_app_number] => 754607 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3953324 [patent_doc_number] => 05977562 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Electro-optical device' [patent_app_type] => 1 [patent_app_number] => 8/748887 [patent_app_country] => US [patent_app_date] => 1996-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 22 [patent_no_of_words] => 7976 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/977/05977562.pdf [firstpage_image] =>[orig_patent_app_number] => 748887 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3957737 [patent_doc_number] => 05930654 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'Method of producing semiconductor devices including a step of dicing a semiconductor wafer while covering the semiconductor wafer by a tape' [patent_app_type] => 1 [patent_app_number] => 8/746552 [patent_app_country] => US [patent_app_date] => 1996-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 4728 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/930/05930654.pdf [firstpage_image] =>[orig_patent_app_number] => 746552 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3896150 [patent_doc_number] => 05897331 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-27 [patent_title] => 'High efficiency low cost thin film silicon solar cell design and method for making' [patent_app_type] => 1 [patent_app_number] => 8/745951 [patent_app_country] => US [patent_app_date] => 1996-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 10210 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/897/05897331.pdf [firstpage_image] =>[orig_patent_app_number] => 745951 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3855908 [patent_doc_number] => 05705434 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-06 [patent_title] => 'Method of manufacturing thermoelectric conversion module' [patent_app_type] => 1 [patent_app_number] => 8/744599 [patent_app_country] => US [patent_app_date] => 1996-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 3183 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/705/05705434.pdf [firstpage_image] =>[orig_patent_app_number] => 744599 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3885404 [patent_doc_number] => 05723376 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-03 [patent_title] => 'Method of manufacturing SiC semiconductor device having double oxide film formation to reduce film defects' [patent_app_type] => 1 [patent_app_number] => 8/745958 [patent_app_country] => US [patent_app_date] => 1996-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 4740 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/723/05723376.pdf [firstpage_image] =>[orig_patent_app_number] => 745958 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3885702 [patent_doc_number] => 05714394 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-03 [patent_title] => 'Method of making an ultra high density NAND gate using a stacked transistor arrangement' [patent_app_type] => 1 [patent_app_number] => 8/745029 [patent_app_country] => US [patent_app_date] => 1996-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 6656 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/714/05714394.pdf [firstpage_image] =>[orig_patent_app_number] => 745029 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4254731 [patent_doc_number] => 06222245 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'High capacity capacitor and corresponding manufacturing process' [patent_app_type] => 1 [patent_app_number] => 8/739997 [patent_app_country] => US [patent_app_date] => 1996-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2479 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/222/06222245.pdf [firstpage_image] =>[orig_patent_app_number] => 739997 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3813751 [patent_doc_number] => 05789312 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-04 [patent_title] => 'Method of fabricating mid-gap metal gates compatible with ultra-thin dielectrics' [patent_app_type] => 1 [patent_app_number] => 8/739765 [patent_app_country] => US [patent_app_date] => 1996-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3557 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/789/05789312.pdf [firstpage_image] =>[orig_patent_app_number] => 739765 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3726718 [patent_doc_number] => 05702962 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-30 [patent_title] => 'Fabrication process for a static induction transistor' [patent_app_type] => 1 [patent_app_number] => 8/739953 [patent_app_country] => US [patent_app_date] => 1996-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 45 [patent_no_of_words] => 9458 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/702/05702962.pdf [firstpage_image] =>[orig_patent_app_number] => 739953 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3767286 [patent_doc_number] => 05733709 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-31 [patent_title] => 'Semiconductor processing method of forming a field effect transistor' [patent_app_type] => 1 [patent_app_number] => 8/740162 [patent_app_country] => US [patent_app_date] => 1996-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2505 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/733/05733709.pdf [firstpage_image] =>[orig_patent_app_number] => 740162 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3767773 [patent_doc_number] => 05773315 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-30 [patent_title] => 'Product wafer yield prediction method employing a unit cell approach' [patent_app_type] => 1 [patent_app_number] => 8/736831 [patent_app_country] => US [patent_app_date] => 1996-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 10424 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 315 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/773/05773315.pdf [firstpage_image] =>[orig_patent_app_number] => 736831 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3877128 [patent_doc_number] => 05804470 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-08 [patent_title] => 'Method of making a selective epitaxial growth circuit load element' [patent_app_type] => 1 [patent_app_number] => 8/735463 [patent_app_country] => US [patent_app_date] => 1996-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3575 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/804/05804470.pdf [firstpage_image] =>[orig_patent_app_number] => 735463 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3957838 [patent_doc_number] => 05930661 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'Substrate clamp design for minimizing substrate to clamp sticking during thermal processing of thermally flowable layers' [patent_app_type] => 1 [patent_app_number] => 8/732580 [patent_app_country] => US [patent_app_date] => 1996-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 5479 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/930/05930661.pdf [firstpage_image] =>[orig_patent_app_number] => 732580 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3858474 [patent_doc_number] => 05792675 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-11 [patent_title] => 'Method for manufacturing an accelerometer sensor of crystalline material' [patent_app_type] => 1 [patent_app_number] => 8/730257 [patent_app_country] => US [patent_app_date] => 1996-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2195 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/792/05792675.pdf [firstpage_image] =>[orig_patent_app_number] => 730257 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3815663 [patent_doc_number] => 05770518 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-23 [patent_title] => 'Semiconductor device and method of manufacturing without undercutting conductive lines' [patent_app_type] => 1 [patent_app_number] => 8/728225 [patent_app_country] => US [patent_app_date] => 1996-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3859 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/770/05770518.pdf [firstpage_image] =>[orig_patent_app_number] => 728225 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3935359 [patent_doc_number] => 05972782 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'Ultrasound treatment of polycrystalline silicon thin films to enhance hydrogenation' [patent_app_type] => 1 [patent_app_number] => 8/727963 [patent_app_country] => US [patent_app_date] => 1996-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 4617 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/972/05972782.pdf [firstpage_image] =>[orig_patent_app_number] => 727963 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3888814 [patent_doc_number] => 05834330 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-10 [patent_title] => 'Selective etch method for II-VI semiconductors' [patent_app_type] => 1 [patent_app_number] => 8/726731 [patent_app_country] => US [patent_app_date] => 1996-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2949 [patent_no_of_claims] => 115 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/834/05834330.pdf [firstpage_image] =>[orig_patent_app_number] => 726731 [rel_patent_id] =>[rel_patent_doc_number] =>)