
Kevin L. Lee
Examiner (ID: 14152, Phone: (571)272-4915 , Office: P/3753 )
| Most Active Art Unit | 3753 |
| Art Unit(s) | 3753, 3407, 3727, 2899 |
| Total Applications | 3737 |
| Issued Applications | 3236 |
| Pending Applications | 189 |
| Abandoned Applications | 321 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3785910
[patent_doc_number] => 05736436
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-04-07
[patent_title] => 'Method of making a thin film transistor panel'
[patent_app_type] => 1
[patent_app_number] => 8/561045
[patent_app_country] => US
[patent_app_date] => 1995-11-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 24
[patent_no_of_words] => 4767
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/736/05736436.pdf
[firstpage_image] =>[orig_patent_app_number] => 561045
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/561045 | Method of making a thin film transistor panel | Nov 19, 1995 | Issued |
| 08/557800 | LINEWIDTH CONTROL APPARATUS AND METHOD | Nov 19, 1995 | Abandoned |
Array
(
[id] => 3620488
[patent_doc_number] => 05641700
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-06-24
[patent_title] => 'Charge coupled device with edge aligned implants and electrodes'
[patent_app_type] => 1
[patent_app_number] => 8/558629
[patent_app_country] => US
[patent_app_date] => 1995-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 23
[patent_no_of_words] => 7667
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/641/05641700.pdf
[firstpage_image] =>[orig_patent_app_number] => 558629
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/558629 | Charge coupled device with edge aligned implants and electrodes | Nov 13, 1995 | Issued |
Array
(
[id] => 3847530
[patent_doc_number] => 05719075
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-02-17
[patent_title] => 'Method of making a planar charge coupled device with edge aligned implants and electrodes connected with overlying metal'
[patent_app_type] => 1
[patent_app_number] => 8/556551
[patent_app_country] => US
[patent_app_date] => 1995-11-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 15
[patent_no_of_words] => 6903
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 273
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/719/05719075.pdf
[firstpage_image] =>[orig_patent_app_number] => 556551
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/556551 | Method of making a planar charge coupled device with edge aligned implants and electrodes connected with overlying metal | Nov 12, 1995 | Issued |
Array
(
[id] => 3552285
[patent_doc_number] => 05573961
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-11-12
[patent_title] => 'Method of making a body contact for a MOSFET device fabricated in an SOI layer'
[patent_app_type] => 1
[patent_app_number] => 8/565201
[patent_app_country] => US
[patent_app_date] => 1995-11-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 2239
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 433
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/573/05573961.pdf
[firstpage_image] =>[orig_patent_app_number] => 565201
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/565201 | Method of making a body contact for a MOSFET device fabricated in an SOI layer | Nov 8, 1995 | Issued |
Array
(
[id] => 4046459
[patent_doc_number] => 05869371
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-02-09
[patent_title] => 'Structure and process for reducing the on-resistance of mos-gated power devices'
[patent_app_type] => 1
[patent_app_number] => 8/552383
[patent_app_country] => US
[patent_app_date] => 1995-11-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 21
[patent_no_of_words] => 5290
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 276
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/869/05869371.pdf
[firstpage_image] =>[orig_patent_app_number] => 552383
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/552383 | Structure and process for reducing the on-resistance of mos-gated power devices | Nov 2, 1995 | Issued |
Array
(
[id] => 3619837
[patent_doc_number] => 05688700
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-11-18
[patent_title] => 'Method of forming a field effect transistor'
[patent_app_type] => 1
[patent_app_number] => 8/552855
[patent_app_country] => US
[patent_app_date] => 1995-11-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 16
[patent_no_of_words] => 2763
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 271
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/688/05688700.pdf
[firstpage_image] =>[orig_patent_app_number] => 552855
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/552855 | Method of forming a field effect transistor | Nov 2, 1995 | Issued |
Array
(
[id] => 3740335
[patent_doc_number] => 05786235
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-07-28
[patent_title] => 'Process for depositing a surface-wide layer through a mask and optionally closing said mask'
[patent_app_type] => 1
[patent_app_number] => 8/537915
[patent_app_country] => US
[patent_app_date] => 1995-10-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 10
[patent_no_of_words] => 3238
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 157
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/786/05786235.pdf
[firstpage_image] =>[orig_patent_app_number] => 537915
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/537915 | Process for depositing a surface-wide layer through a mask and optionally closing said mask | Oct 30, 1995 | Issued |
Array
(
[id] => 3727956
[patent_doc_number] => 05652159
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-07-29
[patent_title] => 'Thin film transistor having improved switching characteristic'
[patent_app_type] => 1
[patent_app_number] => 8/548559
[patent_app_country] => US
[patent_app_date] => 1995-10-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 38
[patent_no_of_words] => 8110
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/652/05652159.pdf
[firstpage_image] =>[orig_patent_app_number] => 548559
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/548559 | Thin film transistor having improved switching characteristic | Oct 25, 1995 | Issued |
Array
(
[id] => 3656402
[patent_doc_number] => 05658806
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-08-19
[patent_title] => 'Method for fabricating thin-film transistor with bottom-gate or dual-gate configuration'
[patent_app_type] => 1
[patent_app_number] => 8/547715
[patent_app_country] => US
[patent_app_date] => 1995-10-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 11
[patent_no_of_words] => 2160
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/658/05658806.pdf
[firstpage_image] =>[orig_patent_app_number] => 547715
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/547715 | Method for fabricating thin-film transistor with bottom-gate or dual-gate configuration | Oct 25, 1995 | Issued |
Array
(
[id] => 3812239
[patent_doc_number] => 05710052
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-01-20
[patent_title] => 'Scanning spreading resistance probe'
[patent_app_type] => 1
[patent_app_number] => 8/543979
[patent_app_country] => US
[patent_app_date] => 1995-10-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 12
[patent_no_of_words] => 3476
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/710/05710052.pdf
[firstpage_image] =>[orig_patent_app_number] => 543979
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/543979 | Scanning spreading resistance probe | Oct 16, 1995 | Issued |
Array
(
[id] => 3791263
[patent_doc_number] => 05780320
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-07-14
[patent_title] => 'Method of manufacturing a semiconductor laser including two sets of dicing grooves'
[patent_app_type] => 1
[patent_app_number] => 8/542029
[patent_app_country] => US
[patent_app_date] => 1995-10-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 35
[patent_no_of_words] => 5519
[patent_no_of_claims] => 56
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 338
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/780/05780320.pdf
[firstpage_image] =>[orig_patent_app_number] => 542029
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/542029 | Method of manufacturing a semiconductor laser including two sets of dicing grooves | Oct 11, 1995 | Issued |
Array
(
[id] => 3983155
[patent_doc_number] => 05891253
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-04-06
[patent_title] => 'Corrosion resistant apparatus'
[patent_app_type] => 1
[patent_app_number] => 8/542367
[patent_app_country] => US
[patent_app_date] => 1995-10-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 3885
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 67
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/891/05891253.pdf
[firstpage_image] =>[orig_patent_app_number] => 542367
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/542367 | Corrosion resistant apparatus | Oct 11, 1995 | Issued |
Array
(
[id] => 3620424
[patent_doc_number] => 05641695
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-06-24
[patent_title] => 'Method of forming a silicon carbide JFET'
[patent_app_type] => 1
[patent_app_number] => 8/538063
[patent_app_country] => US
[patent_app_date] => 1995-10-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 3
[patent_no_of_words] => 1424
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/641/05641695.pdf
[firstpage_image] =>[orig_patent_app_number] => 538063
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/538063 | Method of forming a silicon carbide JFET | Oct 1, 1995 | Issued |
| 08/534247 | METHOD OF MANUFACTURING MOS TRANSISTOR DEVICE | Sep 25, 1995 | Abandoned |
Array
(
[id] => 3681793
[patent_doc_number] => 05633187
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-05-27
[patent_title] => 'Process for fabricating read-only memory cells'
[patent_app_type] => 1
[patent_app_number] => 8/532305
[patent_app_country] => US
[patent_app_date] => 1995-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 8
[patent_no_of_words] => 2782
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 273
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/633/05633187.pdf
[firstpage_image] =>[orig_patent_app_number] => 532305
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/532305 | Process for fabricating read-only memory cells | Sep 21, 1995 | Issued |
Array
(
[id] => 3964985
[patent_doc_number] => 05885880
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-03-23
[patent_title] => 'Bipolar transistor device and method for manufacturing the same'
[patent_app_type] => 1
[patent_app_number] => 8/529213
[patent_app_country] => US
[patent_app_date] => 1995-09-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 39
[patent_figures_cnt] => 39
[patent_no_of_words] => 10795
[patent_no_of_claims] => 43
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/885/05885880.pdf
[firstpage_image] =>[orig_patent_app_number] => 529213
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/529213 | Bipolar transistor device and method for manufacturing the same | Sep 14, 1995 | Issued |
Array
(
[id] => 3759293
[patent_doc_number] => 05843796
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-12-01
[patent_title] => 'Method of making an insulated gate bipolar transistor with high-energy P+ i m'
[patent_app_type] => 1
[patent_app_number] => 8/526427
[patent_app_country] => US
[patent_app_date] => 1995-09-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 6835
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 520
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/843/05843796.pdf
[firstpage_image] =>[orig_patent_app_number] => 526427
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/526427 | Method of making an insulated gate bipolar transistor with high-energy P+ i m | Sep 10, 1995 | Issued |
Array
(
[id] => 3768741
[patent_doc_number] => 05733806
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-03-31
[patent_title] => 'Method for forming a self-aligned semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 8/523705
[patent_app_country] => US
[patent_app_date] => 1995-09-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 2812
[patent_no_of_claims] => 18
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[patent_words_short_claim] => 87
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/733/05733806.pdf
[firstpage_image] =>[orig_patent_app_number] => 523705
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/523705 | Method for forming a self-aligned semiconductor device | Sep 4, 1995 | Issued |
Array
(
[id] => 3693841
[patent_doc_number] => 05650335
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-07-22
[patent_title] => 'Method of fabricating a semiconductor device including a process of adjusting fet characteristics after forming the fet'
[patent_app_type] => 1
[patent_app_number] => 8/523511
[patent_app_country] => US
[patent_app_date] => 1995-09-01
[patent_effective_date] => 0000-00-00
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[patent_no_of_words] => 3292
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/650/05650335.pdf
[firstpage_image] =>[orig_patent_app_number] => 523511
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/523511 | Method of fabricating a semiconductor device including a process of adjusting fet characteristics after forming the fet | Aug 31, 1995 | Issued |