Kevin L. Lee

Array ( [id] => 3657710 [patent_doc_number] => 05591650 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-07 [patent_title] => 'Method of making a body contacted SOI MOSFET' [patent_app_type] => 1 [patent_app_number] => 8/488683 [patent_app_country] => US [patent_app_date] => 1995-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 2396 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 503 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/591/05591650.pdf [firstpage_image] =>[orig_patent_app_number] => 488683 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3655984 [patent_doc_number] => 05622878 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-22 [patent_title] => 'Method of making an integration of high voltage lateral MOS devices in low voltage CMOS architecture using CMOS-compatible process steps' [patent_app_type] => 1 [patent_app_number] => 8/474647 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 7158 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/622/05622878.pdf [firstpage_image] =>[orig_patent_app_number] => 474647 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4237558 [patent_doc_number] => 06080592 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-27 [patent_title] => 'Method of making layered superlattice materials for ferroelectric, high dielectric constant, integrated circuit applications' [patent_app_type] => 1 [patent_app_number] => 8/477331 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 60 [patent_no_of_words] => 22365 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/080/06080592.pdf [firstpage_image] =>[orig_patent_app_number] => 477331 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3646993 [patent_doc_number] => 05683919 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-04 [patent_title] => 'Transistor and circuit incorporating same' [patent_app_type] => 1 [patent_app_number] => 8/473623 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 21 [patent_no_of_words] => 4063 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/683/05683919.pdf [firstpage_image] =>[orig_patent_app_number] => 473623 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3812282 [patent_doc_number] => 05710055 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-20 [patent_title] => 'Method of making PMOSFETs having indium or gallium doped buried channels and n+ polysilicon gates and CMOS devices fabricated therefrom' [patent_app_type] => 1 [patent_app_number] => 8/478133 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 2754 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/710/05710055.pdf [firstpage_image] =>[orig_patent_app_number] => 478133 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3660210 [patent_doc_number] => 05656517 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-12 [patent_title] => 'Windowed source and segmented backgate contact linear geometry source cell for power DMOS processes' [patent_app_type] => 1 [patent_app_number] => 8/473837 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 4207 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/656/05656517.pdf [firstpage_image] =>[orig_patent_app_number] => 473837 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3723482 [patent_doc_number] => 05681768 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-28 [patent_title] => 'Transistor having reduced hot carrier implantation' [patent_app_type] => 1 [patent_app_number] => 8/482329 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 15 [patent_no_of_words] => 4080 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/681/05681768.pdf [firstpage_image] =>[orig_patent_app_number] => 482329 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4000742 [patent_doc_number] => 05858844 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-12 [patent_title] => 'Method for construction and fabrication of submicron field-effect transistors by optimization of poly oxide process' [patent_app_type] => 1 [patent_app_number] => 8/485871 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 2263 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/858/05858844.pdf [firstpage_image] =>[orig_patent_app_number] => 485871 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3705300 [patent_doc_number] => 05654225 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-05 [patent_title] => 'Integrated structure active clamp for the protection of power devices against overvoltages, and manufacturing process thereof' [patent_app_type] => 1 [patent_app_number] => 8/473792 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 3193 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/654/05654225.pdf [firstpage_image] =>[orig_patent_app_number] => 473792 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3621267 [patent_doc_number] => 05593908 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-14 [patent_title] => 'Lateral resonant tunneling' [patent_app_type] => 1 [patent_app_number] => 8/485249 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 37 [patent_no_of_words] => 5178 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/593/05593908.pdf [firstpage_image] =>[orig_patent_app_number] => 485249 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3765756 [patent_doc_number] => 05742089 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-21 [patent_title] => 'Growth of low dislocation density HGCDTE detector structures' [patent_app_type] => 1 [patent_app_number] => 8/484802 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4117 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/742/05742089.pdf [firstpage_image] =>[orig_patent_app_number] => 484802 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3646021 [patent_doc_number] => 05637532 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-10 [patent_title] => 'Interconnect decoupling scheme' [patent_app_type] => 1 [patent_app_number] => 8/481164 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3057 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/637/05637532.pdf [firstpage_image] =>[orig_patent_app_number] => 481164 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3705003 [patent_doc_number] => 05654205 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-05 [patent_title] => 'Apparatus and method for depositing particles onto a wafer' [patent_app_type] => 1 [patent_app_number] => 8/476113 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3101 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/654/05654205.pdf [firstpage_image] =>[orig_patent_app_number] => 476113 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3657551 [patent_doc_number] => 05627085 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-06 [patent_title] => 'Method for hydrogenating a polycrystal silicon layer of a thin film transistor' [patent_app_type] => 1 [patent_app_number] => 8/499651 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2660 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/627/05627085.pdf [firstpage_image] =>[orig_patent_app_number] => 499651 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3661022 [patent_doc_number] => 05624860 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-29 [patent_title] => 'Vertical field effect transistor and method' [patent_app_type] => 1 [patent_app_number] => 8/485539 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 28 [patent_no_of_words] => 5496 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/624/05624860.pdf [firstpage_image] =>[orig_patent_app_number] => 485539 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3657941 [patent_doc_number] => 05627111 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-06 [patent_title] => 'Electron emitting device and process for producing the same' [patent_app_type] => 1 [patent_app_number] => 8/472111 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 2440 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/627/05627111.pdf [firstpage_image] =>[orig_patent_app_number] => 472111 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3633488 [patent_doc_number] => 05631181 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-20 [patent_title] => 'Method of making a monolithic diode array' [patent_app_type] => 1 [patent_app_number] => 8/479953 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 2685 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/631/05631181.pdf [firstpage_image] =>[orig_patent_app_number] => 479953 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3621281 [patent_doc_number] => 05593909 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-14 [patent_title] => 'Method for fabricating a MOS transistor having an offset resistance' [patent_app_type] => 1 [patent_app_number] => 8/467715 [patent_app_country] => US [patent_app_date] => 1995-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 3048 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/593/05593909.pdf [firstpage_image] =>[orig_patent_app_number] => 467715 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3622958 [patent_doc_number] => 05612255 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-18 [patent_title] => 'One dimensional silicon quantum wire devices and the method of manufacture thereof' [patent_app_type] => 1 [patent_app_number] => 8/466315 [patent_app_country] => US [patent_app_date] => 1995-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 2105 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/612/05612255.pdf [firstpage_image] =>[orig_patent_app_number] => 466315 [rel_patent_id] =>[rel_patent_doc_number] =>)