Kevin L. Lee

Array ( [id] => 3514227 [patent_doc_number] => 05512517 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-30 [patent_title] => 'Self-aligned gate sidewall spacer in a corrugated FET and method of making same' [patent_app_type] => 1 [patent_app_number] => 8/428739 [patent_app_country] => US [patent_app_date] => 1995-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 20 [patent_no_of_words] => 2786 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/512/05512517.pdf [firstpage_image] =>[orig_patent_app_number] => 428739 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3601422 [patent_doc_number] => 05578508 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-26 [patent_title] => 'Vertical power MOSFET and process of fabricating the same' [patent_app_type] => 1 [patent_app_number] => 8/426233 [patent_app_country] => US [patent_app_date] => 1995-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 3235 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/578/05578508.pdf [firstpage_image] =>[orig_patent_app_number] => 426233 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3587734 [patent_doc_number] => 05516717 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-14 [patent_title] => 'Method for manufacturing electrostatic discharge devices' [patent_app_type] => 1 [patent_app_number] => 8/424887 [patent_app_country] => US [patent_app_date] => 1995-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 1901 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/516/05516717.pdf [firstpage_image] =>[orig_patent_app_number] => 424887 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3488402 [patent_doc_number] => 05560780 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-01 [patent_title] => 'Protective coating for dielectric material on wafer support used in integrated circuit processing apparatus and method of forming same' [patent_app_type] => 1 [patent_app_number] => 8/420620 [patent_app_country] => US [patent_app_date] => 1995-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2960 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 16 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/560/05560780.pdf [firstpage_image] =>[orig_patent_app_number] => 420620 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3768815 [patent_doc_number] => 05733811 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-31 [patent_title] => 'Method for fabricating vertical type mosfet' [patent_app_type] => 1 [patent_app_number] => 8/420715 [patent_app_country] => US [patent_app_date] => 1995-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 27 [patent_no_of_words] => 2155 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/733/05733811.pdf [firstpage_image] =>[orig_patent_app_number] => 420715 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3622590 [patent_doc_number] => 05612230 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-18 [patent_title] => 'Process for manufacturing a semiconductor device by applying a non-single-crystalline material on a sidewall inside of an opening portion for growing a single-crystalline semiconductor body' [patent_app_type] => 1 [patent_app_number] => 8/417901 [patent_app_country] => US [patent_app_date] => 1995-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 59 [patent_figures_cnt] => 96 [patent_no_of_words] => 21060 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/612/05612230.pdf [firstpage_image] =>[orig_patent_app_number] => 417901 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3588768 [patent_doc_number] => 05585298 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-17 [patent_title] => 'Self aligned antiblooming structure for solid state image sensors' [patent_app_type] => 1 [patent_app_number] => 8/415113 [patent_app_country] => US [patent_app_date] => 1995-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 15 [patent_no_of_words] => 4445 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/585/05585298.pdf [firstpage_image] =>[orig_patent_app_number] => 415113 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3726840 [patent_doc_number] => 05702971 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-30 [patent_title] => 'Self-aligned LOD antiblooming structure for solid-state imagers' [patent_app_type] => 1 [patent_app_number] => 8/414545 [patent_app_country] => US [patent_app_date] => 1995-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 3178 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/702/05702971.pdf [firstpage_image] =>[orig_patent_app_number] => 414545 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3656016 [patent_doc_number] => 05622880 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-22 [patent_title] => 'Method of making a low power, high performance junction transistor' [patent_app_type] => 1 [patent_app_number] => 8/414621 [patent_app_country] => US [patent_app_date] => 1995-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 9131 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/622/05622880.pdf [firstpage_image] =>[orig_patent_app_number] => 414621 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4012053 [patent_doc_number] => 05879979 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-09 [patent_title] => 'Method of manufacturing a semiconductor device containing CMOS elements' [patent_app_type] => 1 [patent_app_number] => 8/412939 [patent_app_country] => US [patent_app_date] => 1995-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 36 [patent_no_of_words] => 9677 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/879/05879979.pdf [firstpage_image] =>[orig_patent_app_number] => 412939 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3695529 [patent_doc_number] => 05595918 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-21 [patent_title] => 'Process for manufacture of P channel MOS-gated device' [patent_app_type] => 1 [patent_app_number] => 8/409181 [patent_app_country] => US [patent_app_date] => 1995-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 2053 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/595/05595918.pdf [firstpage_image] =>[orig_patent_app_number] => 409181 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3622794 [patent_doc_number] => 05612244 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-18 [patent_title] => 'Insulated gate semiconductor device having a cavity under a portion of a gate structure and method of manufacture' [patent_app_type] => 1 [patent_app_number] => 8/408657 [patent_app_country] => US [patent_app_date] => 1995-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4243 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/612/05612244.pdf [firstpage_image] =>[orig_patent_app_number] => 408657 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3525944 [patent_doc_number] => 05541132 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-30 [patent_title] => 'Insulated gate semiconductor device and method of manufacture' [patent_app_type] => 1 [patent_app_number] => 8/408653 [patent_app_country] => US [patent_app_date] => 1995-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 9055 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/541/05541132.pdf [firstpage_image] =>[orig_patent_app_number] => 408653 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3504947 [patent_doc_number] => 05514610 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-07 [patent_title] => 'Method of making an optimized code ion implantation procedure for read only memory devices' [patent_app_type] => 1 [patent_app_number] => 8/405717 [patent_app_country] => US [patent_app_date] => 1995-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1675 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/514/05514610.pdf [firstpage_image] =>[orig_patent_app_number] => 405717 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3504857 [patent_doc_number] => 05514604 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-07 [patent_title] => 'Vertical channel silicon carbide metal-oxide-semiconductor field effect transistor with self-aligned gate for microwave and power applications, and method of making' [patent_app_type] => 1 [patent_app_number] => 8/405618 [patent_app_country] => US [patent_app_date] => 1995-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 25 [patent_no_of_words] => 5076 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 293 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/514/05514604.pdf [firstpage_image] =>[orig_patent_app_number] => 405618 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3931768 [patent_doc_number] => 05952694 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-14 [patent_title] => 'Semiconductor device made using processing from both sides of a workpiece' [patent_app_type] => 1 [patent_app_number] => 8/403580 [patent_app_country] => US [patent_app_date] => 1995-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 86 [patent_no_of_words] => 14101 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/952/05952694.pdf [firstpage_image] =>[orig_patent_app_number] => 403580 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3601478 [patent_doc_number] => 05578512 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-26 [patent_title] => 'Power MESFET structure and fabrication process with high breakdown voltage and enhanced source to drain current' [patent_app_type] => 1 [patent_app_number] => 8/401017 [patent_app_country] => US [patent_app_date] => 1995-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3118 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/578/05578512.pdf [firstpage_image] =>[orig_patent_app_number] => 401017 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3622283 [patent_doc_number] => 05602050 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-11 [patent_title] => 'Method of making a semiconductor device with conductors on stepped substrate having planar upper surfaces' [patent_app_type] => 1 [patent_app_number] => 8/396799 [patent_app_country] => US [patent_app_date] => 1995-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 32 [patent_no_of_words] => 7411 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/602/05602050.pdf [firstpage_image] =>[orig_patent_app_number] => 396799 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3566658 [patent_doc_number] => 05484743 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-16 [patent_title] => 'Self-aligned anti-punchthrough implantation process' [patent_app_type] => 1 [patent_app_number] => 8/394587 [patent_app_country] => US [patent_app_date] => 1995-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 2818 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/484/05484743.pdf [firstpage_image] =>[orig_patent_app_number] => 394587 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3601396 [patent_doc_number] => 05578506 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-26 [patent_title] => 'Method of fabricating improved lateral Silicon-On-Insulator (SOI) power device' [patent_app_type] => 1 [patent_app_number] => 8/395237 [patent_app_country] => US [patent_app_date] => 1995-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2764 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/578/05578506.pdf [firstpage_image] =>[orig_patent_app_number] => 395237 [rel_patent_id] =>[rel_patent_doc_number] =>)