Kevin L. Lee

Array ( [id] => 3556785 [patent_doc_number] => 05502009 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-26 [patent_title] => 'Method for fabricating gate oxide layers of different thicknesses' [patent_app_type] => 1 [patent_app_number] => 8/389247 [patent_app_country] => US [patent_app_date] => 1995-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 2383 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/502/05502009.pdf [firstpage_image] =>[orig_patent_app_number] => 389247 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3581246 [patent_doc_number] => 05580795 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-03 [patent_title] => 'Fabrication method for integrated structure such as photoconductive impedance-matched infrared detector with heterojunction blocking contacts' [patent_app_type] => 1 [patent_app_number] => 8/389549 [patent_app_country] => US [patent_app_date] => 1995-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 3105 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/580/05580795.pdf [firstpage_image] =>[orig_patent_app_number] => 389549 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3585934 [patent_doc_number] => 05552330 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-03 [patent_title] => 'Resonant tunneling fet and methods of fabrication' [patent_app_type] => 1 [patent_app_number] => 8/386171 [patent_app_country] => US [patent_app_date] => 1995-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3161 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/552/05552330.pdf [firstpage_image] =>[orig_patent_app_number] => 386171 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3612734 [patent_doc_number] => 05534454 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-09 [patent_title] => 'Method of producing a semiconductor device having accurate current detection' [patent_app_type] => 1 [patent_app_number] => 8/385553 [patent_app_country] => US [patent_app_date] => 1995-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 4666 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/534/05534454.pdf [firstpage_image] =>[orig_patent_app_number] => 385553 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3768572 [patent_doc_number] => 05733794 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-31 [patent_title] => 'Process for forming a semiconductor device with ESD protection' [patent_app_type] => 1 [patent_app_number] => 8/384177 [patent_app_country] => US [patent_app_date] => 1995-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2649 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/733/05733794.pdf [firstpage_image] =>[orig_patent_app_number] => 384177 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3622682 [patent_doc_number] => 05612236 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-18 [patent_title] => 'Method of forming a silicon semiconductor device using doping during deposition of polysilicon' [patent_app_type] => 1 [patent_app_number] => 8/383946 [patent_app_country] => US [patent_app_date] => 1995-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2592 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/612/05612236.pdf [firstpage_image] =>[orig_patent_app_number] => 383946 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3825881 [patent_doc_number] => 05783491 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-21 [patent_title] => 'Method of forming a truck MOS gate or a power semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/382581 [patent_app_country] => US [patent_app_date] => 1995-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 61 [patent_figures_cnt] => 85 [patent_no_of_words] => 10411 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/783/05783491.pdf [firstpage_image] =>[orig_patent_app_number] => 382581 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3633448 [patent_doc_number] => 05631178 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-20 [patent_title] => 'Method for forming a stable semiconductor device having an arsenic doped ROM portion' [patent_app_type] => 1 [patent_app_number] => 8/381387 [patent_app_country] => US [patent_app_date] => 1995-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2776 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/631/05631178.pdf [firstpage_image] =>[orig_patent_app_number] => 381387 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3570691 [patent_doc_number] => 05538910 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-23 [patent_title] => 'Method of making a narrow gate electrode for a field effect transistor' [patent_app_type] => 1 [patent_app_number] => 8/377617 [patent_app_country] => US [patent_app_date] => 1995-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 51 [patent_no_of_words] => 8323 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 358 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/538/05538910.pdf [firstpage_image] =>[orig_patent_app_number] => 377617 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3529521 [patent_doc_number] => 05583064 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-10 [patent_title] => 'Semiconductor device and process for formation thereof' [patent_app_type] => 1 [patent_app_number] => 8/376517 [patent_app_country] => US [patent_app_date] => 1995-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 21 [patent_no_of_words] => 4401 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/583/05583064.pdf [firstpage_image] =>[orig_patent_app_number] => 376517 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3532839 [patent_doc_number] => 05556801 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-17 [patent_title] => 'Method of making a planar charge coupled device with edge aligned implants and interconnected electrodes' [patent_app_type] => 1 [patent_app_number] => 8/376699 [patent_app_country] => US [patent_app_date] => 1995-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 25 [patent_no_of_words] => 6934 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/556/05556801.pdf [firstpage_image] =>[orig_patent_app_number] => 376699 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3611413 [patent_doc_number] => 05565368 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-15 [patent_title] => 'High density integrated semiconductor device and manufacturing method thereof' [patent_app_type] => 1 [patent_app_number] => 8/370289 [patent_app_country] => US [patent_app_date] => 1995-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 38 [patent_no_of_words] => 5042 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/565/05565368.pdf [firstpage_image] =>[orig_patent_app_number] => 370289 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3656041 [patent_doc_number] => 05622882 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-22 [patent_title] => 'Method of making a CMOS dynamic random-access memory (DRAM)' [patent_app_type] => 1 [patent_app_number] => 8/367533 [patent_app_country] => US [patent_app_date] => 1994-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 30 [patent_no_of_words] => 7652 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/622/05622882.pdf [firstpage_image] =>[orig_patent_app_number] => 367533 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3624852 [patent_doc_number] => 05620911 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-15 [patent_title] => 'Method for fabricating a metal field effect transistor having a recessed gate' [patent_app_type] => 1 [patent_app_number] => 8/365293 [patent_app_country] => US [patent_app_date] => 1994-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 2736 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 310 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/620/05620911.pdf [firstpage_image] =>[orig_patent_app_number] => 365293 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3539261 [patent_doc_number] => 05480814 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-02 [patent_title] => 'Process of making a polysilicon barrier layer in a self-aligned contact module' [patent_app_type] => 1 [patent_app_number] => 8/365049 [patent_app_country] => US [patent_app_date] => 1994-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 2586 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/480/05480814.pdf [firstpage_image] =>[orig_patent_app_number] => 365049 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3543997 [patent_doc_number] => 05554568 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-10 [patent_title] => 'Polysilicon trench and buried polysilicon wall device structures' [patent_app_type] => 1 [patent_app_number] => 8/365047 [patent_app_country] => US [patent_app_date] => 1994-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 1993 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/554/05554568.pdf [firstpage_image] =>[orig_patent_app_number] => 365047 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3509555 [patent_doc_number] => 05563082 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-08 [patent_title] => 'Method of manufacturing a Xmos insulated transistor' [patent_app_type] => 1 [patent_app_number] => 8/362919 [patent_app_country] => US [patent_app_date] => 1994-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 2151 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/563/05563082.pdf [firstpage_image] =>[orig_patent_app_number] => 362919 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3519010 [patent_doc_number] => 05529947 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-25 [patent_title] => 'Semiconductor device with clad substrate and fabrication process therefor' [patent_app_type] => 1 [patent_app_number] => 8/356509 [patent_app_country] => US [patent_app_date] => 1994-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 22 [patent_no_of_words] => 3232 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/529/05529947.pdf [firstpage_image] =>[orig_patent_app_number] => 356509 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3647755 [patent_doc_number] => 05639683 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-17 [patent_title] => 'Structure and method for intergrating microwave components on a substrate' [patent_app_type] => 1 [patent_app_number] => 8/347931 [patent_app_country] => US [patent_app_date] => 1994-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2881 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/639/05639683.pdf [firstpage_image] =>[orig_patent_app_number] => 347931 [rel_patent_id] =>[rel_patent_doc_number] =>)