| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 3663495
[patent_doc_number] => 05668045
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-09-16
[patent_title] => 'Process for stripping outer edge of BESOI wafers'
[patent_app_type] => 1
[patent_app_number] => 8/346695
[patent_app_country] => US
[patent_app_date] => 1994-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 13
[patent_no_of_words] => 2756
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/668/05668045.pdf
[firstpage_image] =>[orig_patent_app_number] => 346695
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/346695 | Process for stripping outer edge of BESOI wafers | Nov 29, 1994 | Issued |
Array
(
[id] => 3665378
[patent_doc_number] => 05599722
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-02-04
[patent_title] => 'SOI semiconductor device and method of producing same wherein warpage is reduced in the semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 8/346255
[patent_app_country] => US
[patent_app_date] => 1994-11-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 11
[patent_no_of_words] => 3646
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 152
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/599/05599722.pdf
[firstpage_image] =>[orig_patent_app_number] => 346255
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/346255 | SOI semiconductor device and method of producing same wherein warpage is reduced in the semiconductor device | Nov 22, 1994 | Issued |
| 08/340341 | SEMICONDUCTOR APPARATUS AND METHOD OF MANUFACTURING THE SAME | Nov 13, 1994 | Abandoned |
Array
(
[id] => 3443915
[patent_doc_number] => 05420046
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-05-30
[patent_title] => 'Method for manufacturing optically triggered lateral thyristor'
[patent_app_type] => 1
[patent_app_number] => 8/339293
[patent_app_country] => US
[patent_app_date] => 1994-11-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 10
[patent_no_of_words] => 3456
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 368
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/420/05420046.pdf
[firstpage_image] =>[orig_patent_app_number] => 339293
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/339293 | Method for manufacturing optically triggered lateral thyristor | Nov 9, 1994 | Issued |
Array
(
[id] => 3525957
[patent_doc_number] => 05541133
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-07-30
[patent_title] => 'Method of manufacturing insulated electrodes in a semiconductor device and semiconductor device manufactured by such a method'
[patent_app_type] => 1
[patent_app_number] => 8/336147
[patent_app_country] => US
[patent_app_date] => 1994-11-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 5
[patent_no_of_words] => 2200
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 252
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/541/05541133.pdf
[firstpage_image] =>[orig_patent_app_number] => 336147
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/336147 | Method of manufacturing insulated electrodes in a semiconductor device and semiconductor device manufactured by such a method | Nov 7, 1994 | Issued |
Array
(
[id] => 3539606
[patent_doc_number] => 05480838
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-01-02
[patent_title] => 'Method of manufacturing a semiconductor device having vertical transistor with tubular double-gate'
[patent_app_type] => 1
[patent_app_number] => 8/334083
[patent_app_country] => US
[patent_app_date] => 1994-11-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 33
[patent_figures_cnt] => 65
[patent_no_of_words] => 9343
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/480/05480838.pdf
[firstpage_image] =>[orig_patent_app_number] => 334083
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/334083 | Method of manufacturing a semiconductor device having vertical transistor with tubular double-gate | Nov 3, 1994 | Issued |
| 08/333517 | METHOD FOR PRODUCING A CONTACT HOLE TO A DOPED REGION | Nov 1, 1994 | Abandoned |
Array
(
[id] => 3515109
[patent_doc_number] => 05576227
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-11-19
[patent_title] => 'Process for fabricating a recessed gate MOS device'
[patent_app_type] => 1
[patent_app_number] => 8/333219
[patent_app_country] => US
[patent_app_date] => 1994-11-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 1786
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 150
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/576/05576227.pdf
[firstpage_image] =>[orig_patent_app_number] => 333219
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/333219 | Process for fabricating a recessed gate MOS device | Nov 1, 1994 | Issued |
Array
(
[id] => 3428229
[patent_doc_number] => 05455187
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-10-03
[patent_title] => 'Method of making a semiconductor device with a metallic layer coupled to a lower region of a substrate and metallic layer coupled to a lower region of a semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 8/331783
[patent_app_country] => US
[patent_app_date] => 1994-11-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 27
[patent_no_of_words] => 11694
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 273
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/455/05455187.pdf
[firstpage_image] =>[orig_patent_app_number] => 331783
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/331783 | Method of making a semiconductor device with a metallic layer coupled to a lower region of a substrate and metallic layer coupled to a lower region of a semiconductor device | Oct 31, 1994 | Issued |
Array
(
[id] => 3412075
[patent_doc_number] => 05443992
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-08-22
[patent_title] => 'Method for manufacturing an integrated circuit having at least one MOS transistor'
[patent_app_type] => 1
[patent_app_number] => 8/332733
[patent_app_country] => US
[patent_app_date] => 1994-11-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 4203
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 161
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/443/05443992.pdf
[firstpage_image] =>[orig_patent_app_number] => 332733
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/332733 | Method for manufacturing an integrated circuit having at least one MOS transistor | Oct 31, 1994 | Issued |
Array
(
[id] => 3695596
[patent_doc_number] => 05595922
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-01-21
[patent_title] => 'Process for thickening selective gate oxide regions'
[patent_app_type] => 1
[patent_app_number] => 8/330655
[patent_app_country] => US
[patent_app_date] => 1994-10-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 5
[patent_no_of_words] => 2188
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 208
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/595/05595922.pdf
[firstpage_image] =>[orig_patent_app_number] => 330655
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/330655 | Process for thickening selective gate oxide regions | Oct 27, 1994 | Issued |
Array
(
[id] => 3665455
[patent_doc_number] => 05599728
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-02-04
[patent_title] => 'Method of fabricating a self-aligned high speed MOSFET device'
[patent_app_type] => 1
[patent_app_number] => 8/330505
[patent_app_country] => US
[patent_app_date] => 1994-10-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 15
[patent_no_of_words] => 2117
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 199
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/599/05599728.pdf
[firstpage_image] =>[orig_patent_app_number] => 330505
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/330505 | Method of fabricating a self-aligned high speed MOSFET device | Oct 27, 1994 | Issued |
Array
(
[id] => 3611541
[patent_doc_number] => 05565377
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-10-15
[patent_title] => 'Process for forming retrograde profiles in silicon'
[patent_app_type] => 1
[patent_app_number] => 8/329959
[patent_app_country] => US
[patent_app_date] => 1994-10-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2471
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/565/05565377.pdf
[firstpage_image] =>[orig_patent_app_number] => 329959
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/329959 | Process for forming retrograde profiles in silicon | Oct 26, 1994 | Issued |
Array
(
[id] => 3657811
[patent_doc_number] => 05591657
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-01-07
[patent_title] => 'Semiconductor apparatus manufacturing method employing gate side wall self-aligning for masking'
[patent_app_type] => 1
[patent_app_number] => 8/329943
[patent_app_country] => US
[patent_app_date] => 1994-10-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 23
[patent_no_of_words] => 12176
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 153
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/591/05591657.pdf
[firstpage_image] =>[orig_patent_app_number] => 329943
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/329943 | Semiconductor apparatus manufacturing method employing gate side wall self-aligning for masking | Oct 25, 1994 | Issued |
Array
(
[id] => 3588703
[patent_doc_number] => 05585294
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-12-17
[patent_title] => 'Method of fabricating lateral double diffused MOS (LDMOS) transistors'
[patent_app_type] => 1
[patent_app_number] => 8/324057
[patent_app_country] => US
[patent_app_date] => 1994-10-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 16
[patent_no_of_words] => 6886
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 173
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/585/05585294.pdf
[firstpage_image] =>[orig_patent_app_number] => 324057
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/324057 | Method of fabricating lateral double diffused MOS (LDMOS) transistors | Oct 13, 1994 | Issued |
Array
(
[id] => 3488579
[patent_doc_number] => 05470767
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-11-28
[patent_title] => 'Method of making field effect transistor'
[patent_app_type] => 1
[patent_app_number] => 8/321851
[patent_app_country] => US
[patent_app_date] => 1994-10-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 20
[patent_no_of_words] => 5081
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 321
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/470/05470767.pdf
[firstpage_image] =>[orig_patent_app_number] => 321851
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/321851 | Method of making field effect transistor | Oct 13, 1994 | Issued |
Array
(
[id] => 3107176
[patent_doc_number] => 05407854
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-04-18
[patent_title] => 'ESD protection of ISFET sensors'
[patent_app_type] => 1
[patent_app_number] => 8/322226
[patent_app_country] => US
[patent_app_date] => 1994-10-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 4411
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/407/05407854.pdf
[firstpage_image] =>[orig_patent_app_number] => 322226
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/322226 | ESD protection of ISFET sensors | Oct 12, 1994 | Issued |
Array
(
[id] => 3486991
[patent_doc_number] => 05474940
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-12-12
[patent_title] => 'Method of fabricating a semiconductor device having shallow junctions in source-drain regions and a gate electrode with a low resistance silicide layer'
[patent_app_type] => 1
[patent_app_number] => 8/320828
[patent_app_country] => US
[patent_app_date] => 1994-10-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 2103
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 308
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/474/05474940.pdf
[firstpage_image] =>[orig_patent_app_number] => 320828
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/320828 | Method of fabricating a semiconductor device having shallow junctions in source-drain regions and a gate electrode with a low resistance silicide layer | Oct 6, 1994 | Issued |
Array
(
[id] => 3646916
[patent_doc_number] => 05629217
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-05-13
[patent_title] => 'Method and apparatus for SOI transistor'
[patent_app_type] => 1
[patent_app_number] => 8/319150
[patent_app_country] => US
[patent_app_date] => 1994-10-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 55
[patent_no_of_words] => 9633
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/629/05629217.pdf
[firstpage_image] =>[orig_patent_app_number] => 319150
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/319150 | Method and apparatus for SOI transistor | Oct 5, 1994 | Issued |
Array
(
[id] => 3552090
[patent_doc_number] => 05492852
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-02-20
[patent_title] => 'Method for fabricating a solid imaging device having improved smear and breakdown voltage characteristics'
[patent_app_type] => 1
[patent_app_number] => 8/319101
[patent_app_country] => US
[patent_app_date] => 1994-10-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 33
[patent_no_of_words] => 6577
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 287
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/492/05492852.pdf
[firstpage_image] =>[orig_patent_app_number] => 319101
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/319101 | Method for fabricating a solid imaging device having improved smear and breakdown voltage characteristics | Oct 5, 1994 | Issued |