Search

Kevin L. Lee

Examiner (ID: 14152, Phone: (571)272-4915 , Office: P/3753 )

Most Active Art Unit
3753
Art Unit(s)
3753, 3407, 3727, 2899
Total Applications
3737
Issued Applications
3236
Pending Applications
189
Abandoned Applications
321

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3608127 [patent_doc_number] => 05589423 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-31 [patent_title] => 'Process for fabricating a non-silicided region in an integrated circuit' [patent_app_type] => 1 [patent_app_number] => 8/317045 [patent_app_country] => US [patent_app_date] => 1994-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 4522 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/589/05589423.pdf [firstpage_image] =>[orig_patent_app_number] => 317045 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/317045
Process for fabricating a non-silicided region in an integrated circuit Oct 2, 1994 Issued
Array ( [id] => 3102044 [patent_doc_number] => 05447876 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-05 [patent_title] => 'Method of making a diamond shaped gate mesh for cellular MOS transistor array' [patent_app_type] => 1 [patent_app_number] => 8/313471 [patent_app_country] => US [patent_app_date] => 1994-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4820 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/447/05447876.pdf [firstpage_image] =>[orig_patent_app_number] => 313471 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/313471
Method of making a diamond shaped gate mesh for cellular MOS transistor array Sep 26, 1994 Issued
Array ( [id] => 3517031 [patent_doc_number] => 05486483 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-23 [patent_title] => 'Method of forming closely spaced metal electrodes in a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/312845 [patent_app_country] => US [patent_app_date] => 1994-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 7 [patent_no_of_words] => 3134 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/486/05486483.pdf [firstpage_image] =>[orig_patent_app_number] => 312845 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/312845
Method of forming closely spaced metal electrodes in a semiconductor device Sep 26, 1994 Issued
Array ( [id] => 3838580 [patent_doc_number] => 05744373 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-28 [patent_title] => 'Method of manufacturing a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/310001 [patent_app_country] => US [patent_app_date] => 1994-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 20 [patent_no_of_words] => 12200 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/744/05744373.pdf [firstpage_image] =>[orig_patent_app_number] => 310001 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/310001
Method of manufacturing a semiconductor device Sep 19, 1994 Issued
Array ( [id] => 3589108 [patent_doc_number] => 05496750 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-05 [patent_title] => 'Elevated source/drain junction metal oxide semiconductor field-effect transistor using blanket silicon deposition' [patent_app_type] => 1 [patent_app_number] => 8/308771 [patent_app_country] => US [patent_app_date] => 1994-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 1995 [patent_no_of_claims] => 59 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/496/05496750.pdf [firstpage_image] =>[orig_patent_app_number] => 308771 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/308771
Elevated source/drain junction metal oxide semiconductor field-effect transistor using blanket silicon deposition Sep 18, 1994 Issued
Array ( [id] => 3705313 [patent_doc_number] => 05654226 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-05 [patent_title] => 'Wafer bonding for power devices' [patent_app_type] => 1 [patent_app_number] => 8/305435 [patent_app_country] => US [patent_app_date] => 1994-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 9 [patent_no_of_words] => 2339 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/654/05654226.pdf [firstpage_image] =>[orig_patent_app_number] => 305435 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/305435
Wafer bonding for power devices Sep 6, 1994 Issued
Array ( [id] => 3621370 [patent_doc_number] => 05593915 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-14 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/301183 [patent_app_country] => US [patent_app_date] => 1994-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 27 [patent_no_of_words] => 3797 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/593/05593915.pdf [firstpage_image] =>[orig_patent_app_number] => 301183 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/301183
Method of manufacturing semiconductor device Sep 5, 1994 Issued
Array ( [id] => 3608100 [patent_doc_number] => 05589421 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-31 [patent_title] => 'Method of manufacturing annealed films' [patent_app_type] => 1 [patent_app_number] => 8/300067 [patent_app_country] => US [patent_app_date] => 1994-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 6784 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/589/05589421.pdf [firstpage_image] =>[orig_patent_app_number] => 300067 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/300067
Method of manufacturing annealed films Aug 31, 1994 Issued
Array ( [id] => 3860608 [patent_doc_number] => 05795793 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-18 [patent_title] => 'Process for manufacture of MOS gated device with reduced mask count' [patent_app_type] => 1 [patent_app_number] => 8/299533 [patent_app_country] => US [patent_app_date] => 1994-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 4512 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 17 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/795/05795793.pdf [firstpage_image] =>[orig_patent_app_number] => 299533 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/299533
Process for manufacture of MOS gated device with reduced mask count Aug 31, 1994 Issued
Array ( [id] => 3549750 [patent_doc_number] => 05547895 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-20 [patent_title] => 'Method of fabricating a metal gate MOS transistor with self-aligned first conductivity type source and drain regions and second conductivity type contact regions' [patent_app_type] => 1 [patent_app_number] => 8/299217 [patent_app_country] => US [patent_app_date] => 1994-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 28 [patent_no_of_words] => 2233 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/547/05547895.pdf [firstpage_image] =>[orig_patent_app_number] => 299217 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/299217
Method of fabricating a metal gate MOS transistor with self-aligned first conductivity type source and drain regions and second conductivity type contact regions Aug 30, 1994 Issued
Array ( [id] => 3619104 [patent_doc_number] => 05620525 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-15 [patent_title] => 'Apparatus for supporting a substrate and introducing gas flow doximate to an edge of the substrate' [patent_app_type] => 1 [patent_app_number] => 8/294513 [patent_app_country] => US [patent_app_date] => 1994-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 8224 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/620/05620525.pdf [firstpage_image] =>[orig_patent_app_number] => 294513 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/294513
Apparatus for supporting a substrate and introducing gas flow doximate to an edge of the substrate Aug 22, 1994 Issued
Array ( [id] => 3591269 [patent_doc_number] => 05521105 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-28 [patent_title] => 'Method of forming counter-doped island in power MOSFET' [patent_app_type] => 1 [patent_app_number] => 8/289649 [patent_app_country] => US [patent_app_date] => 1994-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 3578 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/521/05521105.pdf [firstpage_image] =>[orig_patent_app_number] => 289649 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/289649
Method of forming counter-doped island in power MOSFET Aug 11, 1994 Issued
Array ( [id] => 3664615 [patent_doc_number] => 05597758 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-28 [patent_title] => 'Method for forming an electrostatic discharge protection device' [patent_app_type] => 1 [patent_app_number] => 8/283437 [patent_app_country] => US [patent_app_date] => 1994-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2375 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/597/05597758.pdf [firstpage_image] =>[orig_patent_app_number] => 283437 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/283437
Method for forming an electrostatic discharge protection device Jul 31, 1994 Issued
Array ( [id] => 3504973 [patent_doc_number] => 05514612 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-07 [patent_title] => 'Method of making a semiconductor device with integrated RC network and schottky diode' [patent_app_type] => 1 [patent_app_number] => 8/282033 [patent_app_country] => US [patent_app_date] => 1994-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 8191 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/514/05514612.pdf [firstpage_image] =>[orig_patent_app_number] => 282033 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/282033
Method of making a semiconductor device with integrated RC network and schottky diode Jul 27, 1994 Issued
Array ( [id] => 3511692 [patent_doc_number] => 05505779 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-09 [patent_title] => 'Integrated module multi-chamber CVD processing system and its method for processing substrates' [patent_app_type] => 1 [patent_app_number] => 8/280118 [patent_app_country] => US [patent_app_date] => 1994-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 26 [patent_no_of_words] => 17295 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 509 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/505/05505779.pdf [firstpage_image] =>[orig_patent_app_number] => 280118 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/280118
Integrated module multi-chamber CVD processing system and its method for processing substrates Jul 24, 1994 Issued
Array ( [id] => 3549522 [patent_doc_number] => 05571737 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-05 [patent_title] => 'Metal oxide semiconductor device integral with an electro-static discharge circuit' [patent_app_type] => 1 [patent_app_number] => 8/280113 [patent_app_country] => US [patent_app_date] => 1994-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2850 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/571/05571737.pdf [firstpage_image] =>[orig_patent_app_number] => 280113 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/280113
Metal oxide semiconductor device integral with an electro-static discharge circuit Jul 24, 1994 Issued
Array ( [id] => 3517044 [patent_doc_number] => 05486484 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-23 [patent_title] => 'Lateral power MOSFET structure using silicon carbide' [patent_app_type] => 1 [patent_app_number] => 8/255023 [patent_app_country] => US [patent_app_date] => 1994-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 1619 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/486/05486484.pdf [firstpage_image] =>[orig_patent_app_number] => 255023 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/255023
Lateral power MOSFET structure using silicon carbide Jul 24, 1994 Issued
Array ( [id] => 3532873 [patent_doc_number] => 05494494 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-27 [patent_title] => 'Integrated module multi-chamber CVD processing system and its method for processing substrates' [patent_app_type] => 1 [patent_app_number] => 8/280117 [patent_app_country] => US [patent_app_date] => 1994-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 26 [patent_no_of_words] => 17290 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/494/05494494.pdf [firstpage_image] =>[orig_patent_app_number] => 280117 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/280117
Integrated module multi-chamber CVD processing system and its method for processing substrates Jul 24, 1994 Issued
Array ( [id] => 3607952 [patent_doc_number] => 05589410 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-31 [patent_title] => 'An integrated semiconductor device having a buried semiconductor layer and fabrication method thereof' [patent_app_type] => 1 [patent_app_number] => 8/279205 [patent_app_country] => US [patent_app_date] => 1994-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 3214 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/589/05589410.pdf [firstpage_image] =>[orig_patent_app_number] => 279205 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/279205
An integrated semiconductor device having a buried semiconductor layer and fabrication method thereof Jul 21, 1994 Issued
Array ( [id] => 3646930 [patent_doc_number] => 05629218 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-13 [patent_title] => 'Method for forming a field-effect transistor including a mask body and source/drain contacts' [patent_app_type] => 1 [patent_app_number] => 8/278681 [patent_app_country] => US [patent_app_date] => 1994-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 6 [patent_no_of_words] => 2877 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/629/05629218.pdf [firstpage_image] =>[orig_patent_app_number] => 278681 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/278681
Method for forming a field-effect transistor including a mask body and source/drain contacts Jul 20, 1994 Issued
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