
Kevin L. Lee
Examiner (ID: 14152, Phone: (571)272-4915 , Office: P/3753 )
| Most Active Art Unit | 3753 |
| Art Unit(s) | 3753, 3407, 3727, 2899 |
| Total Applications | 3737 |
| Issued Applications | 3236 |
| Pending Applications | 189 |
| Abandoned Applications | 321 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3608127
[patent_doc_number] => 05589423
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-12-31
[patent_title] => 'Process for fabricating a non-silicided region in an integrated circuit'
[patent_app_type] => 1
[patent_app_number] => 8/317045
[patent_app_country] => US
[patent_app_date] => 1994-10-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 10
[patent_no_of_words] => 4522
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/589/05589423.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/317045 | Process for fabricating a non-silicided region in an integrated circuit | Oct 2, 1994 | Issued |
Array
(
[id] => 3102044
[patent_doc_number] => 05447876
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-09-05
[patent_title] => 'Method of making a diamond shaped gate mesh for cellular MOS transistor array'
[patent_app_type] => 1
[patent_app_number] => 8/313471
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[patent_app_date] => 1994-09-27
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[firstpage_image] =>[orig_patent_app_number] => 313471
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Array
(
[id] => 3517031
[patent_doc_number] => 05486483
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[patent_kind] => NA
[patent_issue_date] => 1996-01-23
[patent_title] => 'Method of forming closely spaced metal electrodes in a semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 8/312845
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[patent_app_date] => 1994-09-27
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/312845 | Method of forming closely spaced metal electrodes in a semiconductor device | Sep 26, 1994 | Issued |
Array
(
[id] => 3838580
[patent_doc_number] => 05744373
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-04-28
[patent_title] => 'Method of manufacturing a semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 8/310001
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[patent_app_date] => 1994-09-20
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[firstpage_image] =>[orig_patent_app_number] => 310001
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Array
(
[id] => 3589108
[patent_doc_number] => 05496750
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[patent_kind] => NA
[patent_issue_date] => 1996-03-05
[patent_title] => 'Elevated source/drain junction metal oxide semiconductor field-effect transistor using blanket silicon deposition'
[patent_app_type] => 1
[patent_app_number] => 8/308771
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[patent_app_date] => 1994-09-19
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Array
(
[id] => 3705313
[patent_doc_number] => 05654226
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[patent_issue_date] => 1997-08-05
[patent_title] => 'Wafer bonding for power devices'
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[firstpage_image] =>[orig_patent_app_number] => 305435
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/305435 | Wafer bonding for power devices | Sep 6, 1994 | Issued |
Array
(
[id] => 3621370
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[pdf_file] => patents/05/593/05593915.pdf
[firstpage_image] =>[orig_patent_app_number] => 301183
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Array
(
[id] => 3608100
[patent_doc_number] => 05589421
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-12-31
[patent_title] => 'Method of manufacturing annealed films'
[patent_app_type] => 1
[patent_app_number] => 8/300067
[patent_app_country] => US
[patent_app_date] => 1994-09-01
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[pdf_file] => patents/05/589/05589421.pdf
[firstpage_image] =>[orig_patent_app_number] => 300067
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/300067 | Method of manufacturing annealed films | Aug 31, 1994 | Issued |
Array
(
[id] => 3860608
[patent_doc_number] => 05795793
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-08-18
[patent_title] => 'Process for manufacture of MOS gated device with reduced mask count'
[patent_app_type] => 1
[patent_app_number] => 8/299533
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[firstpage_image] =>[orig_patent_app_number] => 299533
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Array
(
[id] => 3549750
[patent_doc_number] => 05547895
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[patent_kind] => NA
[patent_issue_date] => 1996-08-20
[patent_title] => 'Method of fabricating a metal gate MOS transistor with self-aligned first conductivity type source and drain regions and second conductivity type contact regions'
[patent_app_type] => 1
[patent_app_number] => 8/299217
[patent_app_country] => US
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[pdf_file] => patents/05/547/05547895.pdf
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Array
(
[id] => 3619104
[patent_doc_number] => 05620525
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-04-15
[patent_title] => 'Apparatus for supporting a substrate and introducing gas flow doximate to an edge of the substrate'
[patent_app_type] => 1
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[firstpage_image] =>[orig_patent_app_number] => 294513
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/294513 | Apparatus for supporting a substrate and introducing gas flow doximate to an edge of the substrate | Aug 22, 1994 | Issued |
Array
(
[id] => 3591269
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[patent_title] => 'Method of forming counter-doped island in power MOSFET'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/289649 | Method of forming counter-doped island in power MOSFET | Aug 11, 1994 | Issued |
Array
(
[id] => 3664615
[patent_doc_number] => 05597758
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[patent_issue_date] => 1997-01-28
[patent_title] => 'Method for forming an electrostatic discharge protection device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/283437 | Method for forming an electrostatic discharge protection device | Jul 31, 1994 | Issued |
Array
(
[id] => 3504973
[patent_doc_number] => 05514612
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[patent_title] => 'Method of making a semiconductor device with integrated RC network and schottky diode'
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Array
(
[id] => 3511692
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Array
(
[id] => 3549522
[patent_doc_number] => 05571737
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[patent_issue_date] => 1996-11-05
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Array
(
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Array
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Array
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Array
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