Kevin L. Lee

Array ( [id] => 3657847 [patent_doc_number] => 05591660 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-07 [patent_title] => 'Method of selectively manufacturing a solid state imaging device having either a regular or mirror image output' [patent_app_type] => 1 [patent_app_number] => 8/277585 [patent_app_country] => US [patent_app_date] => 1994-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 33 [patent_no_of_words] => 6822 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/591/05591660.pdf [firstpage_image] =>[orig_patent_app_number] => 277585 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3685497 [patent_doc_number] => 05663075 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-02 [patent_title] => 'Method of fabricating backside illuminated FET optical receiver with gallium arsenide species' [patent_app_type] => 1 [patent_app_number] => 8/274931 [patent_app_country] => US [patent_app_date] => 1994-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 13 [patent_no_of_words] => 5308 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/663/05663075.pdf [firstpage_image] =>[orig_patent_app_number] => 274931 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3539296 [patent_doc_number] => 05480816 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-02 [patent_title] => 'Method of fabricating a bipolar transistor having a link base' [patent_app_type] => 1 [patent_app_number] => 8/273915 [patent_app_country] => US [patent_app_date] => 1994-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 2618 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/480/05480816.pdf [firstpage_image] =>[orig_patent_app_number] => 273915 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3111991 [patent_doc_number] => 05464782 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-07 [patent_title] => 'Method to ensure isolation between source-drain and gate electrode using self aligned silicidation' [patent_app_type] => 1 [patent_app_number] => 8/270765 [patent_app_country] => US [patent_app_date] => 1994-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2369 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 355 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/464/05464782.pdf [firstpage_image] =>[orig_patent_app_number] => 270765 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3597935 [patent_doc_number] => 05559050 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-24 [patent_title] => 'P-MOSFETS with enhanced anomalous narrow channel effect' [patent_app_type] => 1 [patent_app_number] => 8/269857 [patent_app_country] => US [patent_app_date] => 1994-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2142 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/559/05559050.pdf [firstpage_image] =>[orig_patent_app_number] => 269857 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3425187 [patent_doc_number] => 05416032 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-16 [patent_title] => 'Method of making a high conductivity p-plus region for self-aligned, shallow diffused, bipolar transistors' [patent_app_type] => 1 [patent_app_number] => 8/265855 [patent_app_country] => US [patent_app_date] => 1994-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 2403 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 342 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/416/05416032.pdf [firstpage_image] =>[orig_patent_app_number] => 265855 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3410113 [patent_doc_number] => 05460982 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-24 [patent_title] => 'Method for manufacturing lateral bipolar transistors' [patent_app_type] => 1 [patent_app_number] => 8/261263 [patent_app_country] => US [patent_app_date] => 1994-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2551 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/460/05460982.pdf [firstpage_image] =>[orig_patent_app_number] => 261263 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3664402 [patent_doc_number] => 05597743 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-28 [patent_title] => 'Method of manufacturing a field effect transistor with improved isolation between electrode' [patent_app_type] => 1 [patent_app_number] => 8/259149 [patent_app_country] => US [patent_app_date] => 1994-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 4018 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/597/05597743.pdf [firstpage_image] =>[orig_patent_app_number] => 259149 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3447856 [patent_doc_number] => 05424228 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-06-13 [patent_title] => 'Method for fabricating a bipolar transistor with reduced base resistance' [patent_app_type] => 1 [patent_app_number] => 8/258999 [patent_app_country] => US [patent_app_date] => 1994-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 3533 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/424/05424228.pdf [firstpage_image] =>[orig_patent_app_number] => 258999 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3482146 [patent_doc_number] => 05474614 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-12-12 [patent_title] => 'Method and apparatus for releasing a semiconductor wafer from an electrostatic clamp' [patent_app_type] => 1 [patent_app_number] => 8/257993 [patent_app_country] => US [patent_app_date] => 1994-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2659 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/474/05474614.pdf [firstpage_image] =>[orig_patent_app_number] => 257993 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3538047 [patent_doc_number] => 05494844 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-27 [patent_title] => 'Process of fabricating Bi-CMOS integrated circuit device' [patent_app_type] => 1 [patent_app_number] => 8/257529 [patent_app_country] => US [patent_app_date] => 1994-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 4949 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 380 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/494/05494844.pdf [firstpage_image] =>[orig_patent_app_number] => 257529 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3488570 [patent_doc_number] => 05470766 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-28 [patent_title] => 'Efficient method for fabricating optimal BiCMOS N-wells for bipolar and field effect transistors' [patent_app_type] => 1 [patent_app_number] => 8/254817 [patent_app_country] => US [patent_app_date] => 1994-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 5344 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/470/05470766.pdf [firstpage_image] =>[orig_patent_app_number] => 254817 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3621393 [patent_doc_number] => 05593917 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-14 [patent_title] => 'Method of making semiconductor components with electrochemical recovery of the substrate' [patent_app_type] => 1 [patent_app_number] => 8/275445 [patent_app_country] => US [patent_app_date] => 1994-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 9 [patent_no_of_words] => 2553 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/593/05593917.pdf [firstpage_image] =>[orig_patent_app_number] => 275445 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3447867 [patent_doc_number] => 05424229 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-06-13 [patent_title] => 'Method for manufacturing MOSFET having an LDD structure' [patent_app_type] => 1 [patent_app_number] => 8/253836 [patent_app_country] => US [patent_app_date] => 1994-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 4040 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/424/05424229.pdf [firstpage_image] =>[orig_patent_app_number] => 253836 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3924204 [patent_doc_number] => RE036311 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-21 [patent_title] => 'Integrated high-voltage bipolar power transistor and low voltage MOS power transistor structure in the emitter switching configuration and relative manufacturing process' [patent_app_type] => 2 [patent_app_number] => 8/253151 [patent_app_country] => US [patent_app_date] => 1994-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 1862 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 24 [patent_words_short_claim] => 354 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/036/RE036311.pdf [firstpage_image] =>[orig_patent_app_number] => 253151 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3453105 [patent_doc_number] => 05451536 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-19 [patent_title] => 'Power MOSFET transistor' [patent_app_type] => 1 [patent_app_number] => 8/252465 [patent_app_country] => US [patent_app_date] => 1994-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 3843 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/451/05451536.pdf [firstpage_image] =>[orig_patent_app_number] => 252465 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3486930 [patent_doc_number] => 05426059 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-06-20 [patent_title] => 'Method of making vertically stacked bipolar semiconductor structure' [patent_app_type] => 1 [patent_app_number] => 8/249757 [patent_app_country] => US [patent_app_date] => 1994-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 17 [patent_no_of_words] => 3321 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/426/05426059.pdf [firstpage_image] =>[orig_patent_app_number] => 249757 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3488541 [patent_doc_number] => 05470764 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-28 [patent_title] => 'Method of manufacturing a semiconductor device with hydrogen ion intercepting layer' [patent_app_type] => 1 [patent_app_number] => 8/247425 [patent_app_country] => US [patent_app_date] => 1994-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 27 [patent_no_of_words] => 5060 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/470/05470764.pdf [firstpage_image] =>[orig_patent_app_number] => 247425 [rel_patent_id] =>[rel_patent_doc_number] =>)