| Application number | Title of the application | Filing Date | Status |
|---|
Array
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[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-02-28
[patent_title] => 'Method for making collector arrangement for magnetotransistor'
[patent_app_type] => 1
[patent_app_number] => 8/227745
[patent_app_country] => US
[patent_app_date] => 1994-05-18
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Array
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[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-12-03
[patent_title] => 'Method of making SOI Transistor'
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[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 245767
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/245767 | Method of making SOI Transistor | May 17, 1994 | Issued |
Array
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[patent_doc_number] => 05643804
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-07-01
[patent_title] => 'Method of manufacturing a hybrid integrated circuit component having a laminated body'
[patent_app_type] => 1
[patent_app_number] => 8/242813
[patent_app_country] => US
[patent_app_date] => 1994-05-16
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[firstpage_image] =>[orig_patent_app_number] => 242813
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/242813 | Method of manufacturing a hybrid integrated circuit component having a laminated body | May 15, 1994 | Issued |
Array
(
[id] => 3509392
[patent_doc_number] => 05575856
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-11-19
[patent_title] => 'Thermal cycle resistant seal and method of sealing for use with semiconductor wafer processing apparatus'
[patent_app_type] => 1
[patent_app_number] => 8/241192
[patent_app_country] => US
[patent_app_date] => 1994-05-11
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[firstpage_image] =>[orig_patent_app_number] => 241192
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/241192 | Thermal cycle resistant seal and method of sealing for use with semiconductor wafer processing apparatus | May 10, 1994 | Issued |
| 08/234219 | ELECTRIC FIELD EMITTER DEVICE FOR ELECTROSTATIC DISCHARGE PROTECTION OF INTEGRATED CIRCUITS | Apr 27, 1994 | Abandoned |
| 08/232953 | FET HAVING A RECESSED GATE STRUCTURE AND METHOD OF MAKING THE SAME | Apr 24, 1994 | Abandoned |
Array
(
[id] => 3564869
[patent_doc_number] => 05482878
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-01-09
[patent_title] => 'Method for fabricating insulated gate field effect transistor having subthreshold swing'
[patent_app_type] => 1
[patent_app_number] => 8/223393
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[patent_app_date] => 1994-04-04
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[firstpage_image] =>[orig_patent_app_number] => 223393
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/223393 | Method for fabricating insulated gate field effect transistor having subthreshold swing | Apr 3, 1994 | Issued |
| 08/220747 | METHOD OF MAKING A HIGH VOLTAGE RECTIFIER FOR AN INTEGRATED CIRCUIT CHIP | Mar 30, 1994 | Abandoned |
| 08/218411 | SIGNAL CHARGE TRANSFER DEVICES AND METHOD OF MAKING THE SAME | Mar 24, 1994 | Abandoned |
Array
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[id] => 3549435
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[patent_issue_date] => 1996-11-05
[patent_title] => 'Procedure for the manufacture of bipolar transistors without epitaxy and with fully implanted base and collector regions which are self-positioning relative to each other'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/215187 | Procedure for the manufacture of bipolar transistors without epitaxy and with fully implanted base and collector regions which are self-positioning relative to each other | Mar 20, 1994 | Issued |
Array
(
[id] => 3521927
[patent_doc_number] => 05489545
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-02-06
[patent_title] => 'Method of manufacturing an integrated circuit having a charge coupled device and a MOS transistor'
[patent_app_type] => 1
[patent_app_number] => 8/212143
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[firstpage_image] =>[orig_patent_app_number] => 212143
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/212143 | Method of manufacturing an integrated circuit having a charge coupled device and a MOS transistor | Mar 13, 1994 | Issued |
Array
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[id] => 3611482
[patent_doc_number] => 05565373
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-10-15
[patent_title] => 'Method of fabricating an isolation region in a semiconductor device without heat treatment of active regions'
[patent_app_type] => 1
[patent_app_number] => 8/208681
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/209339 | Reduction of base-collector junction parasitic capacitance of heterojunction bipolar transistors | Mar 9, 1994 | Issued |
Array
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[patent_kind] => NA
[patent_issue_date] => 1995-07-18
[patent_title] => 'Method of using corrosion prohibiters in aluminum alloy films'
[patent_app_type] => 1
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/204829 | Method of using corrosion prohibiters in aluminum alloy films | Mar 1, 1994 | Issued |
Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/203129 | Method of forming a novel vertical-gate CMOS compatible lateral bipolar transistor | Feb 27, 1994 | Issued |
Array
(
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[patent_kind] => NA
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/192207 | Method of making a 3-dimensional circuit assembly having electrical contacts that extend through the IC layer | Feb 3, 1994 | Issued |
Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/191963 | Method of making an improved graded collector for inductive loads | Feb 2, 1994 | Issued |