Search

Kevin L. Lee

Examiner (ID: 14152, Phone: (571)272-4915 , Office: P/3753 )

Most Active Art Unit
3753
Art Unit(s)
3753, 3407, 3727, 2899
Total Applications
3737
Issued Applications
3236
Pending Applications
189
Abandoned Applications
321

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3415257 [patent_doc_number] => 05393678 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-28 [patent_title] => 'Method for making collector arrangement for magnetotransistor' [patent_app_type] => 1 [patent_app_number] => 8/227745 [patent_app_country] => US [patent_app_date] => 1994-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5020 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/393/05393678.pdf [firstpage_image] =>[orig_patent_app_number] => 227745 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/227745
Method for making collector arrangement for magnetotransistor May 17, 1994 Issued
Array ( [id] => 3581275 [patent_doc_number] => 05580797 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-03 [patent_title] => 'Method of making SOI Transistor' [patent_app_type] => 1 [patent_app_number] => 8/245767 [patent_app_country] => US [patent_app_date] => 1994-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 55 [patent_no_of_words] => 9632 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/580/05580797.pdf [firstpage_image] =>[orig_patent_app_number] => 245767 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/245767
Method of making SOI Transistor May 17, 1994 Issued
Array ( [id] => 3686800 [patent_doc_number] => 05643804 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-01 [patent_title] => 'Method of manufacturing a hybrid integrated circuit component having a laminated body' [patent_app_type] => 1 [patent_app_number] => 8/242813 [patent_app_country] => US [patent_app_date] => 1994-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 32 [patent_no_of_words] => 12053 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/643/05643804.pdf [firstpage_image] =>[orig_patent_app_number] => 242813 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/242813
Method of manufacturing a hybrid integrated circuit component having a laminated body May 15, 1994 Issued
Array ( [id] => 3509392 [patent_doc_number] => 05575856 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-19 [patent_title] => 'Thermal cycle resistant seal and method of sealing for use with semiconductor wafer processing apparatus' [patent_app_type] => 1 [patent_app_number] => 8/241192 [patent_app_country] => US [patent_app_date] => 1994-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4785 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/575/05575856.pdf [firstpage_image] =>[orig_patent_app_number] => 241192 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/241192
Thermal cycle resistant seal and method of sealing for use with semiconductor wafer processing apparatus May 10, 1994 Issued
08/234219 ELECTRIC FIELD EMITTER DEVICE FOR ELECTROSTATIC DISCHARGE PROTECTION OF INTEGRATED CIRCUITS Apr 27, 1994 Abandoned
08/232953 FET HAVING A RECESSED GATE STRUCTURE AND METHOD OF MAKING THE SAME Apr 24, 1994 Abandoned
Array ( [id] => 3564869 [patent_doc_number] => 05482878 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-09 [patent_title] => 'Method for fabricating insulated gate field effect transistor having subthreshold swing' [patent_app_type] => 1 [patent_app_number] => 8/223393 [patent_app_country] => US [patent_app_date] => 1994-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 5308 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/482/05482878.pdf [firstpage_image] =>[orig_patent_app_number] => 223393 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/223393
Method for fabricating insulated gate field effect transistor having subthreshold swing Apr 3, 1994 Issued
08/220747 METHOD OF MAKING A HIGH VOLTAGE RECTIFIER FOR AN INTEGRATED CIRCUIT CHIP Mar 30, 1994 Abandoned
08/218411 SIGNAL CHARGE TRANSFER DEVICES AND METHOD OF MAKING THE SAME Mar 24, 1994 Abandoned
Array ( [id] => 3549435 [patent_doc_number] => 05571731 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-05 [patent_title] => 'Procedure for the manufacture of bipolar transistors without epitaxy and with fully implanted base and collector regions which are self-positioning relative to each other' [patent_app_type] => 1 [patent_app_number] => 8/215187 [patent_app_country] => US [patent_app_date] => 1994-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 3717 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/571/05571731.pdf [firstpage_image] =>[orig_patent_app_number] => 215187 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/215187
Procedure for the manufacture of bipolar transistors without epitaxy and with fully implanted base and collector regions which are self-positioning relative to each other Mar 20, 1994 Issued
Array ( [id] => 3521927 [patent_doc_number] => 05489545 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-06 [patent_title] => 'Method of manufacturing an integrated circuit having a charge coupled device and a MOS transistor' [patent_app_type] => 1 [patent_app_number] => 8/212143 [patent_app_country] => US [patent_app_date] => 1994-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 3573 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/489/05489545.pdf [firstpage_image] =>[orig_patent_app_number] => 212143 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/212143
Method of manufacturing an integrated circuit having a charge coupled device and a MOS transistor Mar 13, 1994 Issued
Array ( [id] => 3611482 [patent_doc_number] => 05565373 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-15 [patent_title] => 'Method of fabricating an isolation region in a semiconductor device without heat treatment of active regions' [patent_app_type] => 1 [patent_app_number] => 8/208681 [patent_app_country] => US [patent_app_date] => 1994-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 29 [patent_no_of_words] => 11557 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/565/05565373.pdf [firstpage_image] =>[orig_patent_app_number] => 208681 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/208681
Method of fabricating an isolation region in a semiconductor device without heat treatment of active regions Mar 10, 1994 Issued
Array ( [id] => 4058643 [patent_doc_number] => 05913112 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-15 [patent_title] => 'Method of manufacturing an insulated gate field effect semiconductor device having an offset region and/or lightly doped region' [patent_app_type] => 1 [patent_app_number] => 8/209063 [patent_app_country] => US [patent_app_date] => 1994-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 38 [patent_no_of_words] => 8889 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/913/05913112.pdf [firstpage_image] =>[orig_patent_app_number] => 209063 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/209063
Method of manufacturing an insulated gate field effect semiconductor device having an offset region and/or lightly doped region Mar 10, 1994 Issued
Array ( [id] => 3460817 [patent_doc_number] => 05468659 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-21 [patent_title] => 'Reduction of base-collector junction parasitic capacitance of heterojunction bipolar transistors' [patent_app_type] => 1 [patent_app_number] => 8/209339 [patent_app_country] => US [patent_app_date] => 1994-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 14 [patent_no_of_words] => 3204 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/468/05468659.pdf [firstpage_image] =>[orig_patent_app_number] => 209339 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/209339
Reduction of base-collector junction parasitic capacitance of heterojunction bipolar transistors Mar 9, 1994 Issued
Array ( [id] => 3417547 [patent_doc_number] => 05434104 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-07-18 [patent_title] => 'Method of using corrosion prohibiters in aluminum alloy films' [patent_app_type] => 1 [patent_app_number] => 8/204829 [patent_app_country] => US [patent_app_date] => 1994-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4197 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/434/05434104.pdf [firstpage_image] =>[orig_patent_app_number] => 204829 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/204829
Method of using corrosion prohibiters in aluminum alloy films Mar 1, 1994 Issued
Array ( [id] => 3626870 [patent_doc_number] => 05686323 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-11 [patent_title] => 'Method of manufacturing a semiconductor device having an out diffusion preventing film' [patent_app_type] => 1 [patent_app_number] => 8/203591 [patent_app_country] => US [patent_app_date] => 1994-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 1 [patent_no_of_words] => 4045 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/686/05686323.pdf [firstpage_image] =>[orig_patent_app_number] => 203591 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/203591
Method of manufacturing a semiconductor device having an out diffusion preventing film Feb 27, 1994 Issued
Array ( [id] => 2999565 [patent_doc_number] => 05371022 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-12-06 [patent_title] => 'Method of forming a novel vertical-gate CMOS compatible lateral bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 8/203129 [patent_app_country] => US [patent_app_date] => 1994-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 17 [patent_no_of_words] => 1379 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/371/05371022.pdf [firstpage_image] =>[orig_patent_app_number] => 203129 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/203129
Method of forming a novel vertical-gate CMOS compatible lateral bipolar transistor Feb 27, 1994 Issued
Array ( [id] => 3421877 [patent_doc_number] => 05389562 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-14 [patent_title] => 'Double heterojunction bipolar transistor and the method of manufacture therefor' [patent_app_type] => 1 [patent_app_number] => 8/193685 [patent_app_country] => US [patent_app_date] => 1994-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 2580 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/389/05389562.pdf [firstpage_image] =>[orig_patent_app_number] => 193685 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/193685
Double heterojunction bipolar transistor and the method of manufacture therefor Feb 7, 1994 Issued
Array ( [id] => 3522081 [patent_doc_number] => 05489554 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-06 [patent_title] => 'Method of making a 3-dimensional circuit assembly having electrical contacts that extend through the IC layer' [patent_app_type] => 1 [patent_app_number] => 8/192207 [patent_app_country] => US [patent_app_date] => 1994-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3262 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/489/05489554.pdf [firstpage_image] =>[orig_patent_app_number] => 192207 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/192207
Method of making a 3-dimensional circuit assembly having electrical contacts that extend through the IC layer Feb 3, 1994 Issued
Array ( [id] => 3444320 [patent_doc_number] => 05397714 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-03-14 [patent_title] => 'Method of making an improved graded collector for inductive loads' [patent_app_type] => 1 [patent_app_number] => 8/191963 [patent_app_country] => US [patent_app_date] => 1994-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 2846 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/397/05397714.pdf [firstpage_image] =>[orig_patent_app_number] => 191963 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/191963
Method of making an improved graded collector for inductive loads Feb 2, 1994 Issued
Menu